Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

Giuseppina Puzzilli; Bogdan Govoreanu; Fernanda Irrera; Maarten Rosmeulen; Jan Van Houdt

doi:10.1016/j.microrel.2007.01.040

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

Microelectronics Reliability ◽

10.1016/j.microrel.2007.01.040 ◽

2007 ◽

Vol 47 (4-5) ◽

pp. 508-512 ◽

Cited By ~ 27

Author(s):

Giuseppina Puzzilli ◽

Bogdan Govoreanu ◽

Fernanda Irrera ◽

Maarten Rosmeulen ◽

Jan Van Houdt

Keyword(s):

Charge Trapping

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Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

IEICE Transactions on Electronics ◽

10.1093/ietele/e91-c.5.742 ◽

2008 ◽

Vol E91-C (5) ◽

pp. 742-746 ◽

Cited By ~ 1

Author(s):

J. G. YUN ◽

I. H. PARK ◽

S. CHO ◽

J. H. LEE ◽

D.-H. KIM ◽

...

Keyword(s):

Charge Trapping ◽

Channel Memory ◽

Recessed Channel

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On the fly characterization of charge trapping phenomena at GaN/dielectric and GaN/AlGaN/dielectric interfaces using impedance measurements

2015 45th European Solid State Device Research Conference (ESSDERC) ◽

10.1109/essderc.2015.7324716 ◽

2015 ◽

Cited By ~ 2

Author(s):

Roberta Stradiotto ◽

Gregor Pobegen ◽

Clemens Ostermaier ◽

Tibor Grasser

Keyword(s):

Charge Trapping ◽

Impedance Measurements ◽

Dielectric Interfaces

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Thermal characterization of nonlinear charge trapping effects in GaN-FETs

2014 International Workshop on Integrated Nonlinear Microwave and Millimetre-wave Circuits (INMMiC) ◽

10.1109/inmmic.2014.6815103 ◽

2014 ◽

Author(s):

Gian Piero Gibiino ◽

Rafael Cignani ◽

Daniel Niessen ◽

Dominique Schreurs ◽

Alberto Santarelli ◽

...

Keyword(s):

Charge Trapping ◽

Thermal Characterization ◽

Trapping Effects

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Characterization of oxide charge trapping in ultrathin N2O oxide using direct tunneling current

Solid-State Electronics ◽

10.1016/j.sse.2005.11.005 ◽

2006 ◽

Vol 50 (2) ◽

pp. 170-176 ◽

Cited By ~ 1

Author(s):

H. Wong ◽

C.K. Wong ◽

Y. Fu ◽

J.J. Liou

Keyword(s):

Tunneling Current ◽

Charge Trapping ◽

Oxide Charge ◽

Direct Tunneling ◽

Direct Tunneling Current

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Charge Trapping Characterization of LaLuO3/p-Si Interfaces at Cryogenic Temperatures

ECS Transactions ◽

10.1149/06102.0055ecst ◽

2014 ◽

Vol 61 (2) ◽

pp. 55-59

Author(s):

I. P. Tyagulskyy ◽

S. I. Tiagulskyi ◽

A. N. Nazarov ◽

V. S. Lysenko ◽

P. K. Hurley ◽

...

Keyword(s):

Charge Trapping ◽

Cryogenic Temperatures

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Characterization of charge trapping and high-field endurance for 15-nm thermally nitrided oxides

IEEE Transactions on Electron Devices ◽

10.1109/16.69916 ◽

1991 ◽

Vol 38 (2) ◽

pp. 344-354 ◽

Cited By ~ 50

Author(s):

Z.H. Liu ◽

P.T. Lai ◽

Y.C. Cheng

Keyword(s):

High Field ◽

Charge Trapping

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Growth and In-line Characterization of Silicon Nanodots Integrated in Discrete Charge Trapping Non-volatile Memories

MRS Proceedings ◽

10.1557/opl.2011.975 ◽

2011 ◽

Vol 1337 ◽

Cited By ~ 1

Author(s):

J. Amouroux ◽

V. Della Marca ◽

E. Petit ◽

D. Deleruyelle ◽

M. Putero ◽

...

Keyword(s):

Surface Characterization ◽

Chemical Vapor ◽

Charge Trapping ◽

Critical Dimension ◽

Growth Surface ◽

Oxide Surface ◽

Pressure Chemical ◽

Deposition Uniformity ◽

Average Size

ABSTRACTNon-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges.Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Depending on the pre-growth surface treatment, tunnel oxide surface may present either siloxane or silanol groups. SDs deposition relies on a 2–steps process: nucleation by SiH4 and selective growth with SiH2Cl2.In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-dots growth process control. Hence, silicon-dots were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy CDSEM and their average size and density were extracted from image processing. In addition, Haze measurement, generally used for bare silicon surface characterization, was customized to quantify Si-dots deposition uniformity over the wafer. Finally, Haze value was correlated to Si nanodots density and size determined by CDSEM.

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