Growth and In-line Characterization of Silicon Nanodots Integrated in Discrete Charge Trapping Non-volatile Memories

2011 ◽  
Vol 1337 ◽  
Author(s):  
J. Amouroux ◽  
V. Della Marca ◽  
E. Petit ◽  
D. Deleruyelle ◽  
M. Putero ◽  
...  

ABSTRACTNon-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges.Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Depending on the pre-growth surface treatment, tunnel oxide surface may present either siloxane or silanol groups. SDs deposition relies on a 2–steps process: nucleation by SiH4 and selective growth with SiH2Cl2.In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-dots growth process control. Hence, silicon-dots were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy CDSEM and their average size and density were extracted from image processing. In addition, Haze measurement, generally used for bare silicon surface characterization, was customized to quantify Si-dots deposition uniformity over the wafer. Finally, Haze value was correlated to Si nanodots density and size determined by CDSEM.

1997 ◽  
Vol 308-309 ◽  
pp. 594-598 ◽  
Author(s):  
Y.J Mei ◽  
T.C Chang ◽  
J.C Hu ◽  
L.J Chen ◽  
Y.L Yang ◽  
...  

2013 ◽  
Vol 205-206 ◽  
pp. 284-289 ◽  
Author(s):  
David Lysáček ◽  
Petr Kostelník ◽  
Petr Pánek

We report on a novel method of low pressure chemical vapor deposition of polycrystalline silicon layers used for external gettering in silicon substrate for semiconductor applications. The proposed method allowed us to produce layers of polycrystalline silicon with pre-determined residual stress. The method is based on the deposition of a multilayer system formed by two layers. The first layer is intentionally designed to have tensile stress while the second layer has compressive stress. Opposite sign of the residual stresses of the individual layers enables to pre-determine the residual stress of the gettering stack. We used scanning electron microscopy for structural characterization of the layers and intentional contamination for demonstration of the gettering properties. Residual stress of the layers was calculated from the wafer curvature.


2006 ◽  
Vol 89 (11) ◽  
pp. 112119 ◽  
Author(s):  
M. Alevli ◽  
G. Durkaya ◽  
A. Weerasekara ◽  
A. G. U. Perera ◽  
N. Dietz ◽  
...  

2013 ◽  
Vol 16 (1) ◽  
pp. 126-130 ◽  
Author(s):  
Kyu-Hwan Shim ◽  
Hyeon Deok Yang ◽  
Yeon-Ho Kil ◽  
Jong-Han Yang ◽  
Woong-Ki Hong ◽  
...  

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