Support excitation scheme for transient analysis of JEDEC board-level drop test

2006 ◽  
Vol 46 (2-4) ◽  
pp. 626-636 ◽  
Author(s):  
Chang-Lin Yeh ◽  
Yi-Shao Lai
Keyword(s):  
Transient Analysis ◽  
Drop Test ◽  
Excitation Scheme ◽  
Support Excitation ◽  
Board Level

Finite Element Prediction of Stack-Die Packages under Board Level Drop Test

2008 ◽  
Vol 594 ◽  
pp. 169-174
Author(s):  
Hsiang Chen Hsu ◽  
Yu Chia Hsu ◽  
Chan Lin Yeh ◽  
Yi Shao Lai
Keyword(s):  
Solder Joint ◽  
Equivalent Stress ◽  
Drop Test ◽  
Excitation Scheme ◽  
Joint Reliability ◽  
Solder Balls ◽  
Mesh Density ◽  
Parametric Studies ◽  
Support Excitation ◽  
Board Level

The objective of this research is to investigate the solder joint reliability of board-level drop test based on the support excitation scheme incorporated with the submodel technique for stacked-die packages. Three lead-free materials, SAC405 (Sn4Ag0.5Cu), SAC355(Sn3.5Ag0.5Cu) and Sn3.5Ag were used to demonstrate the transient dynamic response for solder balls subject to JEDEC pulse-controlled board-level drop test standard. In order to evaluate the structure of the interested area, a strip model sliced from the full test vehicle is used in this research. In addition, the submodel region is particularly chosen with strip model by performing the cut boundary interpolation. The envelope of equivalent stress for the outermost solder joint off the end of the strip model is plot to show the potential failure mode and mechanism. The cut boundary of submodel is verified and the mesh density of submodel is examined. For a refinery mesh of submodel, parametric studies for structure and material are carried out to investigate the reliability of the outermost solder joint, and the results are summarized as design rules for the development of stacked-die packages.

Optimal design of thin-profile fine-pitch ball grid array package under drop impact test

2011 ◽  
Vol 225 (12) ◽  
pp. 2775-2791 ◽  
Author(s):  
R S Chen ◽  
H E Cheng ◽  
R W Wu ◽  
C H Huang ◽  
W C Liao ◽  
...  
Keyword(s):  
Solder Ball ◽  
Ball Grid Array ◽  
Drop Test ◽  
Circuit Board ◽  
Impact Pulse ◽  
Excitation Scheme ◽  
Thin Profile ◽  
Fine Pitch ◽  
Support Excitation ◽  
The Impact

This article describes the board-level drop reliability of thin-profile fine-pitch ball grid array (TFBGA) subjected to Joint Electron Device Engineering Council (JEDEC) drop test conditions featuring an impact pulse profile with a peak acceleration of 1500  G and a pulse duration of 0.5 ms. The solder ball is assumed to be an elastoplastic model and the other components linear elastic ones. Both the global/local finite element and the finite grid region methods are introduced to improve the accuracy and the convergence during the meshing process. Meanwhile, the contact impact process during the drop test is translated into the effective support excitation load on the printed circuit board (PCB) through the support excitation scheme to simplify the analysis. By means of optimal parameters of the Taguchi robust design, the average stress of the solder ball at the PCB side surface becomes 80.9 MPa, which shows a 57 per cent reduction compared to the original stress of 189.7 MPa. As a result, the impact reliability of the TFBGA package is significantly improved. Finally, the JEDEC drop test is conducted to verify the optimal results obtained by the Taguchi method.

Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages

2006 ◽  
Vol 129 (1) ◽  
pp. 105-108 ◽  
Author(s):  
Yi-Shao Lai ◽  
Chang-Lin Yeh ◽  
Ching-Chun Wang
Keyword(s):  
Time Integration ◽  
Implicit Time ◽  
Wafer Level ◽  
Excitation Scheme ◽  
Implicit Time Integration ◽  
Parametric Studies ◽  
Support Excitation ◽  
Board Level ◽  
Board Level Reliability ◽  
Die Thickness

We present in this paper parametric studies of board-level reliability of wafer-level chip-scale packages subjected to a specific pulse-controlled drop test condition. Eighteen experiment cells, constructed by varying joint pitch, die thickness, and die size, are proposed and examined numerically. The transient analysis follows the support excitation scheme and incorporates an implicit time integration solver. Numerical results indicate that the drop reliability of the package enhances as the die thickness as well as the die size decreases. Moreover, the package with smaller solder joints and a smaller joint pitch suffers a greater drop reliability concern.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

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