Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board

2006 ◽  
Vol 46 (2-4) ◽  
pp. 301-310
Author(s):  
Kun-Hsien Lin ◽  
Ming-Dou Ker
Keyword(s):  
Leakage Current ◽  
Electrostatic Discharge ◽  
Protection Scheme ◽  
Current Path ◽  
Cmos Ic

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

scholarly journals Improvement on Leakage Current Performance of Semiconductor IC Packages by Eliminating ESD Events

2018 ◽  
Vol 6 (5) ◽  
Author(s):  
Frederick Ray Gomez
Keyword(s):  
Product Quality ◽  
Leakage Current ◽  
Integrated Circuit ◽  
Six Sigma ◽  
Electrostatic Discharge ◽  
Assembly Process ◽  
Technical Paper ◽  
High Leakage Current ◽  
Better Than

The technical paper discusses the reduction of high leakage current failures of semiconductor IC (integrated circuit) packages by eliminating the ESD (electrostatic discharge) events during assembly process and ensuring the appropriate machine grounding and ESD controls.  It is imperative to reduce or ideally eliminate the leakage current failures of the device to ensure the product quality, especially as the market becomes more challenging and demanding.  After implementation of the corrective and improvement actions, high leakage current occurrence was reduced from baseline of 5784 ppm to 1567 ppm, better than the six sigma goal of 4715 ppm.

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

2004 ◽  
Vol 39 (10) ◽  
pp. 1778-1782 ◽  
Author(s):  
D. Tremouilles ◽  
M. Bafleur ◽  
G. Bertrand ◽  
N. Nolhier ◽  
N. Mauran ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Design Guidelines ◽  
Protection Scheme ◽  
Esd Protection ◽  
Latch Up

scholarly journals Current path analysis for electrostatic discharge protection

2006 ◽  
Author(s):  
Hung-Yi Liu ◽  
Chung-Wei Lin ◽  
Szu-Jui Chou ◽  
Wei-Ting Tu ◽  
Chih-Hung Liu ◽  
...  
Keyword(s):  
Path Analysis ◽  
Electrostatic Discharge ◽  
Current Path

Origin of reverse leakage current path in edge-defined film-fed growth (001) β-Ga2O3 Schottky barrier diodes observed by high-sensitive emission microscopy

2020 ◽  
Vol 117 (2) ◽  
pp. 022106 ◽  
Author(s):  
Sayleap Sdoeung ◽  
Kohei Sasaki ◽  
Katsumi Kawasaki ◽  
Jun Hirabayashi ◽  
Akito Kuramata ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Leakage Current ◽  
Schottky Barrier Diodes ◽  
Reverse Leakage Current ◽  
Current Path ◽  
Emission Microscopy
Sign in / Sign up

Export Citation Format

Share Document