Latent damage investigation on lateral non-uniform charge generation and stress-induced leakage current in silicon dioxides subjected to low-level electrostatic discharge impulse stressing

1999 ◽  
Author(s):  
P.S. Lim ◽  
W.K. Chim
Keyword(s):  
Leakage Current ◽  
Electrostatic Discharge ◽  
Charge Generation ◽  
Low Level ◽  
Stress Induced Leakage Current ◽  
Damage Investigation

Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky
Keyword(s):  
Leakage Current ◽  
Electrical Performance ◽  
Constant Current ◽  
Continuous Increase ◽  
Current Stress ◽  
Thermal Oxide ◽  
Stress Induced Leakage Current ◽  
Boron Penetration ◽  
Soft Breakdown ◽  
Induced Defects

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

Correlation between stress-induced leakage current and dielectric degradation in ultra-porous SiOCH low-k materials

2015 ◽  
Vol 118 (16) ◽  
pp. 164101 ◽  
Author(s):  
Y. Li ◽  
A. Leśniewska ◽  
O. Varela Pedreira ◽  
J.-F. de Marneffe ◽  
I. Ciofi ◽  
...  
Keyword(s):  
Leakage Current ◽  
Stress Induced Leakage Current ◽  
Low K ◽  
Dielectric Degradation

Transient effects of positive oxide charge on stress-induced leakage current in tunnel oxides

1999 ◽  
Vol 75 (5) ◽  
pp. 734-736 ◽  
Author(s):  
Nian-Kai Zous ◽  
Tahui Wang ◽  
Chih-Chich Yeh ◽  
C. W. Tsai ◽  
Chimoon Huang
Keyword(s):  
Leakage Current ◽  
Transient Effects ◽  
Oxide Charge ◽  
Stress Induced Leakage Current ◽  
Tunnel Oxides

scholarly journals Improvement on Leakage Current Performance of Semiconductor IC Packages by Eliminating ESD Events

2018 ◽  
Vol 6 (5) ◽  
Author(s):  
Frederick Ray Gomez
Keyword(s):  
Product Quality ◽  
Leakage Current ◽  
Integrated Circuit ◽  
Six Sigma ◽  
Electrostatic Discharge ◽  
Assembly Process ◽  
Technical Paper ◽  
High Leakage Current ◽  
Better Than

The technical paper discusses the reduction of high leakage current failures of semiconductor IC (integrated circuit) packages by eliminating the ESD (electrostatic discharge) events during assembly process and ensuring the appropriate machine grounding and ESD controls.  It is imperative to reduce or ideally eliminate the leakage current failures of the device to ensure the product quality, especially as the market becomes more challenging and demanding.  After implementation of the corrective and improvement actions, high leakage current occurrence was reduced from baseline of 5784 ppm to 1567 ppm, better than the six sigma goal of 4715 ppm.

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