An area‐efficient low‐power SCM topology for high performance network‐on Chip (NoC) architecture using an optimized routing design

2018 ◽  
Vol 31 (14) ◽  
Author(s):  
R. Poovendran ◽  
S. Sumathi
Keyword(s):  
Low Power ◽  
High Performance ◽  
Network On Chip ◽  
Routing Design ◽  
On Chip ◽  
Area Efficient

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

3D floorplanning of low-power and area-efficient Network-on-Chip architecture

2011 ◽  
Vol 35 (5) ◽  
pp. 484-495 ◽  
Author(s):  
Licheng Xue ◽  
Feng Shi ◽  
Weixing Ji ◽  
Haroon-Ur-Rashid Khan
Keyword(s):  
Low Power ◽  
Network On Chip ◽  
On Chip ◽  
Area Efficient

ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE

2008 ◽  
Vol 18 (02) ◽  
pp. 239-255 ◽  
Author(s):  
JUN HO BAHN ◽  
SEUNG EUN LEE ◽  
YOON SEOK YANG ◽  
JUNGSOOK YANG ◽  
NADER BAGHERZADEH
Keyword(s):  
Low Power ◽  
High Performance ◽  
Programming Model ◽  
Current System ◽  
Future Generation ◽  
Network On Chip ◽  
System Level ◽  
Processor Array ◽  
Application Mapping ◽  
On Chip

As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to overcome such a limitation, the notion of utilizing Network-on-Chip (NoC) technologies for the future generation of high performance and low power chips for myriad of applications, in particular for wireless communication and multimedia processing, has been of great importance. In order for the NoC technologies to succeed, realistic specifications such as throughput, latency, moderate design complexity, programming model, and design tools are necessary requirements. For this purpose, we have covered some of the key and challenging design issues specific to the NoC architecture such as the router design, network interface (NI) issues, and complete system-level modeling. In this paper, we propose a multi-processor system platform adopting NoC techniques, called NePA (Network-based Processor Array). As a component of system platform, the fundamental NoC techniques including the router architecture and generic NI are defined and implemented adopting low power and clock efficient techniques. Using a high-level cycle-accurate simulation, various parameters relevant to its performance and its systematic modeling are extracted and analyzed. By combining various developed systematic models, we construct the tool chain to pursue hardware/software design tradeoffs necessary for better understanding of the NoC techniques. Finally utilizing implementation of parallel FFT algorithms on the homogeneous NePA, the feasibility and advantages of using NoC techniques are shown.

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