Multi-level cell storage with a modulated current method for phase-change memory using Ge-doped SbTe

2011 ◽  
Vol 11 (2) ◽  
pp. e79-e81 ◽  
Author(s):  
Gang Zhang ◽  
Zhe Wu ◽  
Jeung-Hyun Jeong ◽  
Doo Seok Jeong ◽  
Won Jong Yoo ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Current Method ◽  
Multi Level ◽  
Change Memory ◽  
Cell Storage

scholarly journals Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip

Nanoscale ◽  
2021 ◽  
Author(s):  
Zhitang Song ◽  
Daolin Cai ◽  
Yan Cheng ◽  
Lei Wang ◽  
Shilong Lv ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Chip ◽  
Multi Level ◽  
Change Memory ◽  
Cell Storage

Correction for ‘12-state multi-level cell storage implemented in a 128 Mb phase change memory chip’ by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.

12-state multi-level cell storage implemented in a 128 Mb phase change memory chip

Nanoscale ◽  
2021 ◽  
Author(s):  
Zhitang Song ◽  
Daolin Cai ◽  
Yan Cheng ◽  
Lei Wang ◽  
Shilong Lv ◽  
...  
Keyword(s):  
Artificial Intelligence ◽  
Phase Change ◽  
Phase Change Memory ◽  
Memory Chip ◽  
Multi Level ◽  
Change Memory ◽  
Cell Storage

128 Mb Phase Change Memory (PCM) chips show potential for many applications in artificial intelligence.

A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage

2009 ◽  
Vol 44 (1) ◽  
pp. 217-227 ◽  
Author(s):  
Ferdinando Bedeschi ◽  
Rich Fackenthal ◽  
Claudio Resta ◽  
Enzo Michele Donze ◽  
Meenatchi Jagasivamani ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Multi Level ◽  
Change Memory ◽  
Cell Storage

scholarly journals Speeding Up the Write Operation for Multi-Level Cell Phase Change Memory with Programmable Ramp-Down Current Pulses

Micromachines ◽  
2019 ◽  
Vol 10 (7) ◽  
pp. 461 ◽  
Author(s):  
Chenchen Xie ◽  
Xi Li ◽  
Houpeng Chen ◽  
Yang Li ◽  
Yuanguang Liu ◽  
...  
Keyword(s):  
Phase Change ◽  
Current Source ◽  
Phase Change Memory ◽  
Operation Time ◽  
Access Time ◽  
Fully Differential ◽  
Current Pulses ◽  
Multi Level ◽  
The Impact ◽  
Change Memory

Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce the impact of device-to-device variability at the expense of a greater operation time and more power consumption. This paper proposes a novel write operation for multi-level cell phase change memory: Programmable ramp-down current pulses are utilized to program the RESET initialized memory cells to the expected resistance levels. In addition, a fully differential read circuit with an optional reference current source is employed to complete the readout operation. Eventually, a 2-bit/cell phase change memory chip is presented with a more efficient write operation of a single current pulse and a read access time of 65 ns. Some experiments are implemented to demonstrate the resistance distribution and the drift.

Multi-level phase-change memory with ultralow power consumption and resistance drift

2021 ◽  
Author(s):  
Bin Liu ◽  
Kaiqi Li ◽  
Wanliang Liu ◽  
Jian Zhou ◽  
Liangcai Wu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Phase Change ◽  
Phase Change Memory ◽  
Multi Level ◽  
Ultralow Power ◽  
Change Memory
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