Multi-level phase change memory devices with Ge2Sb2Te5 layers separated by a thermal insulating Ta2O5 barrier layer

2011 ◽  
Vol 110 (12) ◽  
pp. 124517 ◽  
Author(s):  
Ashvini Gyanathan ◽  
Yee-Chia Yeo
Keyword(s):  
Phase Change ◽  
Barrier Layer ◽  
Phase Change Memory ◽  
Memory Devices ◽  
Thermal Insulating ◽  
Multi Level ◽  
Change Memory

Precision of synaptic weights programmed in phase-change memory devices for deep learning inference

2020 ◽  
Author(s):  
S. R. Nandakumar ◽  
Irem Boybat ◽  
Jin-Ping Han ◽  
Stefano Ambrogio ◽  
Praneet Adusumilli ◽  
...  
Keyword(s):  
Deep Learning ◽  
Phase Change ◽  
Phase Change Memory ◽  
Memory Devices ◽  
Change Memory

scholarly journals Speeding Up the Write Operation for Multi-Level Cell Phase Change Memory with Programmable Ramp-Down Current Pulses

Micromachines ◽  
2019 ◽  
Vol 10 (7) ◽  
pp. 461 ◽  
Author(s):  
Chenchen Xie ◽  
Xi Li ◽  
Houpeng Chen ◽  
Yang Li ◽  
Yuanguang Liu ◽  
...  
Keyword(s):  
Phase Change ◽  
Current Source ◽  
Phase Change Memory ◽  
Operation Time ◽  
Access Time ◽  
Fully Differential ◽  
Current Pulses ◽  
Multi Level ◽  
The Impact ◽  
Change Memory

Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce the impact of device-to-device variability at the expense of a greater operation time and more power consumption. This paper proposes a novel write operation for multi-level cell phase change memory: Programmable ramp-down current pulses are utilized to program the RESET initialized memory cells to the expected resistance levels. In addition, a fully differential read circuit with an optional reference current source is employed to complete the readout operation. Eventually, a 2-bit/cell phase change memory chip is presented with a more efficient write operation of a single current pulse and a read access time of 65 ns. Some experiments are implemented to demonstrate the resistance distribution and the drift.

Multi-level phase-change memory with ultralow power consumption and resistance drift

2021 ◽  
Author(s):  
Bin Liu ◽  
Kaiqi Li ◽  
Wanliang Liu ◽  
Jian Zhou ◽  
Liangcai Wu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Phase Change ◽  
Phase Change Memory ◽  
Multi Level ◽  
Ultralow Power ◽  
Change Memory

Modeling of Atomic Migration Phenomena in Phase Change Memory Devices

2015 ◽  
Author(s):  
Luca Crespi ◽  
Andrea Lacaita ◽  
Mattia Boniardi ◽  
Enrico Varesi ◽  
Andrea Ghetti ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Devices ◽  
Change Memory

Phase-change memory devices based on gallium-doped indium oxide

2009 ◽  
Vol 94 (11) ◽  
pp. 113503 ◽  
Author(s):  
S.-L. Wang ◽  
C.-Y. Chen ◽  
M.-K. Hsieh ◽  
W.-C. Lee ◽  
A. H. Kung ◽  
...  
Keyword(s):  
Phase Change ◽  
Indium Oxide ◽  
Phase Change Memory ◽  
Memory Devices ◽  
Change Memory

Holistic Integrated Process Solutions for Patterning Phase Change Memory Devices

2021 ◽  
Vol MA2021-01 (21) ◽  
pp. 846-846
Author(s):  
John Hoang ◽  
Meihua Shen ◽  
Thorsten Lill ◽  
Danna Qian ◽  
Aaron Routzahn ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Devices ◽  
Integrated Process ◽  
Process Solutions ◽  
Change Memory

scholarly journals High Speed Test System of Current Pulse for Phase Change Memory Devices

2019 ◽  
Vol 1237 ◽  
pp. 042064
Author(s):  
Yuhan Wang ◽  
Ziqiang Zeng ◽  
Yuchan Wang ◽  
Xia Xu ◽  
Liangling Gu
Keyword(s):  
Phase Change ◽  
Current Pulse ◽  
High Speed ◽  
Phase Change Memory ◽  
Test System ◽  
Memory Devices ◽  
Speed Test ◽  
Change Memory
Sign in / Sign up

Export Citation Format

Share Document