Effect of hydrogen ion beam treatment on Si nanocrystal/SiO2 superlattice-based memory devices

2016 ◽  
Vol 367 ◽  
pp. 134-139 ◽  
Author(s):  
Sheng-Wen Fu ◽  
Hui-Ju Chen ◽  
Hsuan-Ta Wu ◽  
Bing-Ru Chuang ◽  
Chuan-Feng Shih
Keyword(s):  
Ion Beam ◽  
Hydrogen Ion ◽  
Memory Devices ◽  
Si Nanocrystal ◽  
Ion Beam Treatment

GaAs surface cleaning by low energy hydrogen ion beam treatment

2002 ◽  
Vol 20 (4) ◽  
pp. 1492-1497 ◽  
Author(s):  
N. Razek ◽  
K. Otte ◽  
T. Chassé ◽  
D. Hirsch ◽  
A. Schindler ◽  
...  
Keyword(s):  
Ion Beam ◽  
Surface Cleaning ◽  
Low Energy ◽  
Hydrogen Ion ◽  
Gaas Surface ◽  
Ion Beam Treatment

Photoluminescence of Si nanocrystal memory devices obtained by ion beam synthesis

2005 ◽  
Vol 87 (25) ◽  
pp. 251911 ◽  
Author(s):  
Marzia Carrada ◽  
Anja Wellner ◽  
Vincent Paillard ◽  
Caroline Bonafos ◽  
Hubert Coffin ◽  
...  
Keyword(s):  
Ion Beam ◽  
Memory Devices ◽  
Si Nanocrystal ◽  
Ion Beam Synthesis ◽  
Nanocrystal Memory

scholarly journals Influence of Annealing on the Electrical Properties οf Cz-Si Wafers Previously Subjected to the Hydrogen Ion-Beam Treatment

2011 ◽  
Vol 120 (1) ◽  
pp. 108-110 ◽  
Author(s):  
A. Fedotov ◽  
O. Korolik ◽  
A. Mazanik ◽  
T. Kołtunowicz ◽  
P. Żukowski
Keyword(s):  
Electrical Properties ◽  
Ion Beam ◽  
Hydrogen Ion ◽  
Ion Beam Treatment

Enhancing the electroluminescence efficiency of Si NC/SiO2 superlattice-based light-emitting diodes through hydrogen ion beam treatment

Nanoscale ◽  
2016 ◽  
Vol 8 (13) ◽  
pp. 7155-7162 ◽  
Author(s):  
Sheng-Wen Fu ◽  
Hui-Ju Chen ◽  
Hsuan-Ta Wu ◽  
Shao-Ping Chen ◽  
Chuan-Feng Shih
Keyword(s):  
Light Emitting Diodes ◽  
Ion Beam ◽  
Hydrogen Ion ◽  
Light Emitting ◽  
Ion Beam Treatment ◽  
Novel Method

This paper presents a novel method for enhancing the electroluminescence (EL) efficiency of ten-period silicon-rich oxide (SRO)/SiO2 superlattice-based light-emitting diodes (LEDs).

Effects of annealing conditions on charge storage of Si nanocrystal memory devices obtained by low-energy ion beam synthesis

2003 ◽  
Vol 67-68 ◽  
pp. 629-634 ◽  
Author(s):  
P. Normand ◽  
E. Kapetanakis ◽  
P. Dimitrakis ◽  
D. Skarlatos ◽  
D. Tsoukalas ◽  
...  
Keyword(s):  
Ion Beam ◽  
Low Energy ◽  
Charge Storage ◽  
Memory Devices ◽  
Annealing Conditions ◽  
Si Nanocrystal ◽  
Ion Beam Synthesis ◽  
Nanocrystal Memory

Hydrogen Ion Beam Passivation of Electrically Active Defects in Crystalline Silicon Solar Cells

1985 ◽  
Vol 45 ◽  
Author(s):  
Y.S. Tsuo ◽  
J.B. Milstein ◽  
R.J. Matson
Keyword(s):  
Solar Cells ◽  
Crystalline Silicon ◽  
Ion Beam ◽  
Current Data ◽  
Hydrogen Ion ◽  
Silicon Solar Cells ◽  
Crystalline Silicon Solar Cells ◽  
Ion Beam Treatment ◽  
Electron Beam Induced Current ◽  
Silicon Sheet

ABSTRACTWe have observed significant improvements in the efficiencies of dendritic web and edge-supported-pulling silicon sheet solar cells after hydrogen ion beam passivation for a period of ten minutes or less. We have obtained electron-beam-induced current data that show the hydrogen passivation of dislocations as well as grain boundaries in edge-supportedpulling silicon sheet solar cells. We have studied the effects of the hydrogen ion beam treatment with respect to silicon material damage, silicon sputter rate, introduction of impurities, and changes in reflectance.

High-Throughput, Site-Specific Sample Prep of Ultra-Thin TEM Lamella for Process Metrology and Failure Analysis

2012 ◽  
Author(s):  
Roger Alvis ◽  
Jeff Blackwood ◽  
Sang-Hoon Lee ◽  
Matthew Bray
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Process Monitoring ◽  
High Throughput ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Memory Devices ◽  
Site Specific ◽  
Critical Dimensions ◽  
Tem Lamella

Abstract Semiconductor devices with critical dimensions less than 20nm are now being manufactured in volume. A challenge facing the failure analysis and process-monitoring community is two-fold. The first challenge of TEM sample prep of such small devices is that the basic need to end-point on a feature-of-interest pushes the imaging limit of the instrument being used to prepare the lamella. The second challenge posed by advanced devices is to prepare an artifact-free lamella from non-planar devices such as finFETs as well as from structures incorporating ‘non-traditional’ materials. These challenges are presently overcome in many advanced logic and memory devices in the focused ion beam-based TEM sample preparation processes by inverting the specimen prior to thinning to electron transparency. This paper reports a highthroughput method for the routine preparation of artifact-free TEM lamella of 20nm thickness, or less.

Failure Analysis Strategies for Multistacked Memory Devices with TSV Interconnects

2015 ◽  
Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Memory Devices ◽  
Metallographic Cross Section ◽  
Electron Beam Induced Current ◽  
Thermal Simulations ◽  
Lock In ◽  
Non Destructive

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.

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