Aluminum Metallization Technology for Semiconductor Devices

JOM ◽  
1985 ◽  
Vol 37 (5) ◽  
pp. 55-59 ◽  
Author(s):  
T. J. Garosshen ◽  
T. A. Stephenson ◽  
T. P. Slavin
Keyword(s):  
Semiconductor Devices ◽  
Aluminum Metallization

EFFECT OF PASSIVATING COATINGS ON METALLIZATION TOPOLOGY IN PRODUCTION OF SEMICONDUCTOR DEVICES

2021 ◽  
Vol 0 (4) ◽  
pp. 30-34
Author(s):  
M.V. POTAPOVA ◽  
◽  
M.YU. MAKHMUD-AKHUNOV ◽  
V.N. GOLOVANOV ◽  
K.E. IMESHEV ◽  
...  
Keyword(s):  
Gas Phase ◽  
Silicon Oxide ◽  
Semiconductor Device ◽  
Semiconductor Devices ◽  
Experimental Studies ◽  
Chemical Deposition ◽  
Aluminum Film ◽  
Single Crystal Substrate ◽  
Plasma Chemical ◽  
Aluminum Metallization

The surface quality of the metallized contact pads on the crystal plays an important role in the production of semiconductor devices. This paper presents experimental studies of the effect of a protective passivation film of silicon oxide on the surface structure of aluminum metallization in the field of forming contact pads. Plasma chemical deposition of passivation layer SiO2 from gas phase (PECVD method) was carried out on prepared samples of silicon with aluminum metallization using a high-frequency power source with a frequency of 13.56 MHz. After that, chemical etching of precipitated silicon oxide was carried out to simulate the process of forming contact areas of semiconductor device crystals. The resistance of the metallization surface to plasma processes was studied by raster electron microscopy. It is shown that as a result of the process cycle, defects of the dislocation type are generated in the applied film Al. The nature of the observed defects has been found to be different. The revealed large square-shaped pits with a size of ~ 1 μm at the places where dislocations come to the surface are of a single nature and appear independently of the processes of applying passivation coatings, which is determined by the orienting action of a single-crystal substrate having some low dislocation density. While the second type of defects, shown by the presence of etching pits measuring ~ 100-300 nm, is characterized by a higher surface density. Moreover, the exclusion of the passivation process with silicon oxide did not lead to the appearance of this type of defects, which determined their nature associated with the ion bombardment of the Al layer during the plasma chemical deposition of silicon oxide from the gas phase. It is also shown that a feature of this type of defects is their disorientation both with respect to the first type of defects and with respect to each other. Detection of the structure of the metallization layers was carried out by X-ray diffraction, the results of which show the polycrystallinity of the formed aluminum metallization. The preferred orientation of the aluminum film corresponds to the substrate Si (111).

Selective Wet-Etch of Silicon Nitride Passivation Layers

1998 ◽  
Author(s):  
P. Malberti ◽  
M. Ciappa
Keyword(s):  
Silicon Nitride ◽  
Failure Analysis ◽  
Wide Spectrum ◽  
Semiconductor Devices ◽  
Layer By Layer ◽  
Passivation Layers ◽  
Aluminum Metallization ◽  
Voltage Contrast ◽  
Wet Etch ◽  
First Time

Abstract Selective removal of silicon nitride passivation layers is of major importance in failure analysis of semiconductor devices. Typical applications are: cleaning of the die surface for optical microsccjpy and for removal of superficial contamination, electron microscopy, liquid crystals, voltage contrast, electron beam testing, mechanical microprobing, and . selective layer-by-layer strip. A new wet-etch for silicon nitride passivation layers has been developed, which is fully selective! over aluminum metallization and which preserves full device functionality after passivation removal. For the first time in the failure analysis literature, the chemical recipe and the etching procedure are given in details. This etchant has been experimented for more than two years in many failure analysis laboratories on a wide spectrum of discrete and integrated semiconductor devices, always with excellent results. Its capability and efficiency are illustrated by two failure analysis case histories.

Formation of defects in implanted hipox-structures

1992 ◽  
Vol 50 (2) ◽  
pp. 1406-1407
Author(s):  
Peter Pegler ◽  
N. David Theodore ◽  
Ming Pan
Keyword(s):  
High Pressure ◽  
Cross Section ◽  
Semiconductor Devices ◽  
Silicon Substrates ◽  
Processing Conditions ◽  
Pressure Oxidation ◽  
Deep Trench ◽  
Local Oxidation ◽  
Trench Isolation ◽  
And Behavior

High-pressure oxidation of silicon (HIPOX) is one of various techniques used for electrical-isolation of semiconductor-devices on silicon substrates. Other techniques have included local-oxidation of silicon (LOCOS), poly-buffered LOCOS, deep-trench isolation and separation of silicon by implanted oxygen (SIMOX). Reliable use of HIPOX for device-isolation requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of HIPOX-related stresses in the structures is of interest because structuraldefects, if formed, could electrically degrade devices.This investigation was performed to study the origin and behavior of defects in recessed HIPOX (RHIPOX) structures. The structures were exposed to a boron implant. Samples consisted of (i) RHlPOX'ed strip exposed to a boron implant, (ii) recessed strip prior to HIPOX, but exposed to a boron implant, (iii) test-pad prior to HIPOX, (iv) HIPOX'ed region away from R-HIPOX edge. Cross-section TEM specimens were prepared in the <110> substrate-geometry.

Comparison of ultra high resolution immersion lens CFESEM and TEM for imaging of semiconductor devices

1990 ◽  
Vol 48 (4) ◽  
pp. 622-623
Author(s):  
Terrence Reilly ◽  
Al Pelillo ◽  
Barbara Miner
Keyword(s):  
High Resolution ◽  
Sample Preparation ◽  
Cross Sections ◽  
Semiconductor Devices ◽  
Ion Milling ◽  
Observation Area ◽  
Transmission Electron ◽  
Milling Machines ◽  
Resolution Imaging ◽  
Electron Microscopes

The use of transmission electron microscopes (TEM) has proven to be very valuable in the observation of semiconductor devices. The need for high resolution imaging becomes more important as the devices become smaller and more complex. However, the sample preparation for TEM observation of semiconductor devices have generally proven to be complex and time consuming. The use of ion milling machines usually require a certain degree of expertise and allow a very limited viewing area. Recently, the use of an ultra high resolution "immersion lens" cold cathode field emission scanning electron microscope (CFESEM) has proven to be very useful in the observation of semiconductor devices. Particularly at low accelerating voltages where compositional contrast is increased. The Hitachi S-900 has provided comparable resolution to a 300kV TEM on semiconductor cross sections. Using the CFESEM to supplement work currently being done with high voltage TEMs provides many advantages: sample preparation time is greatly reduced and the observation area has also been increased to 7mm. The larger viewing area provides the operator a much greater area to search for a particular feature of interest. More samples can be imaged on the CFESEM, leaving the TEM for analyses requiring diffraction work and/or detecting the nature of the crystallinity.

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