Reconvergent-fanout-oriented testability measure

1988 ◽  
Vol 3 (1) ◽  
pp. 16-28
Author(s):  
Jianchao Wang ◽  
Daozheng Wei
Keyword(s):  
Reconvergent Fanout

Conflict-Driven Learning in Test Pattern Generation

2011 ◽  
Vol 301-303 ◽  
pp. 1089-1092
Author(s):  
Xin Liu
Keyword(s):  
Test Pattern ◽  
Level Structure ◽  
Conjunctive Normal Form ◽  
Search Space ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Heuristic Learning ◽  
Fundamental Cause ◽  
Reconvergent Fanout ◽  
High Level

SAT-based automatic test pattern generation (ATPG) is built on a SAT-solver, which can be scalable is that it is able to take into account the information of high-level structure of formulas. Paper analyzes specific structure of circuit instances where correlations among signals have been established. This analysis is a heuristic learning method by earlier detecting assignment conflicts. Reconvergent fanout is a fundamental cause of the difficulty in testing generation, because they introduce dependencies in the values that can be assigned to nodes. Paper exploits reconvergent fanout analysis of circuit to gather information about local signal correlation through BDD learning, and then used the learned information in the conjunctive normal form (CNF) clauses to restrict and focus the overall search space of test pattern generation. The experimental results demonstrate the effectiveness of these learning techniques.

An accurate and fast reliability analysis method for combinational circuits

2015 ◽  
Vol 34 (3) ◽  
pp. 979-995 ◽  
Author(s):  
Hamed Zandevakili ◽  
Ali Mahani ◽  
Mohsen Saneei
Keyword(s):  
Computation Time ◽  
Fast Method ◽  
Combinational Circuits ◽  
Content Type ◽  
Evaluation Time ◽  
Probabilistic Description ◽  
Correlation Problem ◽  
Scale Down ◽  
Microelectronics Industry ◽  
Reconvergent Fanout

Purpose – One of the main issues which microelectronics industry encounter is reliability as feature sizes scale down to nano-design level. The purpose of this paper is to provide a probabilistic transfer matrix based to find the accurate and efficient method of finding circuit’s reliability. Design/methodology/approach – The proposed method provides a probabilistic description of faulty behavior and is well-suited to reliability and error susceptibility calculations. The proposed method offers accurate circuit reliability calculations in the presence of reconvergent fanout. Furthermore, a binary probability matrix is used to not only resolve signals correlation problem but also improve the accuracy of the obtained reliability in the presence of reconverging signals. Findings – The results provide the accuracy and computation time of reliability evaluation for ISCAS85 benchmark schemes. Also, simulations have been conducted on some digital circuits involving LGSynth’91 circuits. Simulation results show that proposed solution is a fast method with less complexity and gives an accurate reliability value in comparison with other methods. Originality/value – The proposed method is the only scheme giving the low calculation time with high accuracy compared to other schemes. The library-based method also is able to evaluate the reliability of every scheme independent from its circuit topology. The comparison exhibits that a designer can save its evaluation time in terms of performance and complexity.

scholarly journals Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 187-203
Author(s):  
Miriam Leeser ◽  
Valerie Ohm
Keyword(s):  
State Space ◽  
Space Exploration ◽  
Average Power ◽  
Power Estimation ◽  
The State ◽  
Estimation Methods ◽  
Cmos Circuits ◽  
State Transition Graph ◽  
Reconvergent Fanout ◽  
State Space Exploration

We present a novel method for estimating the power of sequential CMOS circuits. Symbolic probabilistic power estimation with an enumerated state space is used to estimate the average power switched by the circuit. This approach is more accurate than simulation based methods. Automatic circuit partitioning and state space exploration provide improvements in run-time and storage requirements over existing approaches. Circuits are automatically partitioned to improve the execution time and to allow larger circuits to be processed. Spatial correlation is dealt with by minimizing the cutset between partitions which tends to keep areas of reconvergent fanout in the same partition. Circuit partitions can be recombined using our combinational estimation methods which allow the exploitation of knowledge of probabilities of the circuit inputs. We enumerate the state transition graph (STG) incrementally using state space exploration methods developed for formal verification. Portions of the STG are generated on an as-needed basis, and thrown away after they are processed. BDDs are used to compactly represent similar states. This saves significant space in the storage of the STG. Our results show that modeling the state space is imperative for accurate power estimation of sequential circuits, partitioning saves time, and incremental state space exploration saves storage space. This allows us to process larger circuits than would otherwise be possible

Testability measure with reconvergent fanout analysis and its applications

1991 ◽  
Vol 32 (1-5) ◽  
pp. 835-842 ◽  
Author(s):  
Xinli Gu ◽  
Krzysztof Kuchcinski ◽  
Zebo Peng
Keyword(s):  
Reconvergent Fanout
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