Electrical characterization of high purity InGaAsP alloys

1985 ◽  
Vol 14 (6) ◽  
pp. 655-666 ◽  
Author(s):  
J. L. Benchimol ◽  
D. Scalbert} ◽  
M. Quillec
Keyword(s):  
High Purity ◽  
Electrical Characterization ◽  
Ingaasp Alloys

The Effects of Illumination on Point Defects Detected in High Purity Semi-Insulating 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 253-256 ◽  
Author(s):  
Giovanni Alfieri ◽  
Lukas Kranz ◽  
Lars Knoll ◽  
Vinoth Kumar Sundaramoorthy
Keyword(s):  
Point Defects ◽  
High Purity ◽  
Deep Level Transient Spectroscopy ◽  
Optical Pulse ◽  
Deep Level ◽  
Electrical Characterization ◽  
Ionization Energies ◽  
Transient Spectroscopy

The electrical characterization of high-purity semi-insulating 4H-SiC is carried out by means of current deep level transient spectroscopy (I-DLTS). Measurements are performed by employing either an electrical or optical pulse (below/above bandgap). The study performed on as-grown material, either annealed or oxidized, reveals the presence of six levels with ionization energies in the 0.4-1.3 eV range.

Synthesis and characterization of high-purity, single phase hexagonal Bi2Te3 nanostructures

RSC Advances ◽  
2015 ◽  
Vol 5 (32) ◽  
pp. 24930-24935 ◽  
Author(s):  
L. Giri ◽  
G. Mallick ◽  
A. C. Jackson ◽  
M. H. Griep ◽  
S. P. Karna
Keyword(s):  
High Purity ◽  
Solvothermal Synthesis ◽  
Single Phase ◽  
Electrical Characterization ◽  
Synthesis And Characterization ◽  
High Current ◽  
Pellet Surface ◽  
Hexagonal Nanoplates

Schematic solvothermal synthesis of Bi2Te3 (a) producing Bi2Te3 hexagonal nanoplates (TEM) (b) which was converted into pellet (c). The electrical characterization (d) of the Bi2Te3 pellet surface showed significantly high current (more than 100 times) than through the pellet.

Deep Levels Observed in High-Purity Semi-Insulating 4H-SiC

2010 ◽  
Vol 645-648 ◽  
pp. 455-458 ◽  
Author(s):  
Giovanni Alfieri ◽  
Tsunenobu Kimoto ◽  
Gerhard Pensl
Keyword(s):  
High Purity ◽  
Deep Level ◽  
Electrical Characterization ◽  
Current Mode ◽  
Deep Levels ◽  
Light Illumination ◽  
Hall Effect Measurements ◽  
Transient Spectroscopy ◽  
P Type

We report on the electrical characterization of high-purity semi-insulating 4H-SiC after annealing at temperatures between room temperature and 1700 oC by current-mode deep level transient spectroscopy (I-DLTS). I-V and Hall-effect measurements revealed that the investigated substrates possess p-type conductivity. Four deep levels were detected by I-DLTS with activation energies in the 0.15-1.29 eV range. We studied their thermal stability as well as their stability with respect to light illumination.

TEM characterization of WSix films

1994 ◽  
Vol 52 ◽  
pp. 848-849
Author(s):  
V. C. Kannan ◽  
S. M. Merchant ◽  
R. B. Irwin ◽  
A. K. Nanda ◽  
M. Sundahl ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Vapor Deposition ◽  
High Purity ◽  
Physical Vapor Deposition ◽  
Thermal Treatments ◽  
Rapid Thermal Anneal ◽  
Tungsten Silicide ◽  
Tem Characterization ◽  
Metal Silicides

Metal silicides such as WSi2, MoSi2, TiSi2, TaSi2 and CoSi2 have received wide attention in recent years for semiconductor applications in integrated circuits. In this study, we describe the microstructures of WSix films deposited on SiO2 (oxide) and polysilicon (poly) surfaces on Si wafers afterdeposition and rapid thermal anneal (RTA) at several temperatures. The stoichiometry of WSix films was confirmed by Rutherford Backscattering Spectroscopy (RBS). A correlation between the observed microstructure and measured sheet resistance of the films was also obtained.WSix films were deposited by physical vapor deposition (PVD) using magnetron sputteringin a Varian 3180. A high purity tungsten silicide target with a Si:W ratio of 2.85 was used. Films deposited on oxide or poly substrates gave rise to a Si:W ratio of 2.65 as observed by RBS. To simulatethe thermal treatments of subsequent processing procedures, wafers with tungsten silicide films were subjected to RTA (AG Associates Heatpulse 4108) in a N2 ambient for 60 seconds at temperatures ranging from 700° to 1000°C.

Structural and Electrical Characterization of Shaped Beam Laser Recrystallized Polysilicon on Amorphous Substrates

1981 ◽  
Vol 4 ◽  
Author(s):  
T. J. Stultz ◽  
J. F. Gibbons
Keyword(s):  
Grain Size ◽  
Electrical Characterization ◽  
Grain Structure ◽  
Electrical Characteristics ◽  
Shaped Beam ◽  
Beam Laser ◽  
Cw Laser ◽  
Amorphous Substrates ◽  
Circular Beam

ABSTRACTStructural and electrical characterization of laser recrystallized LPCVD silicon films on amorphous substrates using a shaped cw laser beam have been performed. In comparing the results to data obtained using a circular beam, it was found that a significant increase in grain size can be achieved and that the surface morphology of the shaped beam recrystallized material was much smoother. It was also found that whereas circular beam recrystallized material has a random grain structure, shaped beam material is highly oriented with a <100> texture. Finally the electrical characteristics of the recrystallized film were very good when measured in directions parallel to the grain boundaries.

Vapor Deposition Polymerization and Electrical Characterization of TPD Thin Films

2011 ◽  
Vol E94-C (2) ◽  
pp. 157-163 ◽  
Author(s):  
Masakazu MUROYAMA ◽  
Ayako TAJIRI ◽  
Kyoko ICHIDA ◽  
Seiji YOKOKURA ◽  
Kuniaki TANAKA ◽  
...  
Keyword(s):  
Thin Films ◽  
Vapor Deposition ◽  
Electrical Characterization

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

2014 ◽  
Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore
Keyword(s):  
Threshold Voltage ◽  
Crystalline Silicon ◽  
Electrical Characterization ◽  
Visual Defect ◽  
Scanning Capacitance Microscopy ◽  
Device Model ◽  
Graphical Simulation ◽  
Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

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