A hypergraph-based model for port allocation on multiple-register-file VLIW architectures

Andrea Capitanio; Alexandru Nicolau; Nikil Dutt

doi:10.1007/bf02577864

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures

International Journal of Parallel Programming ◽

10.1023/b:ijpp.0000042082.31819.6d ◽

2004 ◽

Vol 32 (6) ◽

pp. 447-474 ◽

Cited By ~ 9

Author(s):

Javier Zalamea ◽

Josep Llosa ◽

Eduard Ayguadé ◽

Mateo Valero

Keyword(s):

Register File ◽

Software And Hardware ◽

Vliw Architectures

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Partitioning of Variables for Multiple-Register-File VLIW Architectures

1994 International Conference on Parallel Processing Vol. 3 ◽

10.1109/icpp.1994.155 ◽

1994 ◽

Cited By ~ 3

Author(s):

Andrea Capitanio ◽

Nikil Dutt ◽

Alexandru Nicolau

Keyword(s):

Register File ◽

Vliw Architectures

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On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage

The Computer Journal ◽

10.1093/comjnl/bxx001 ◽

2017 ◽

Author(s):

Hu He ◽

Xu Yang ◽

Yanjun Zhang

Keyword(s):

Energy Efficiency ◽

Embedded System ◽

Register File ◽

System Usage ◽

Vliw Architectures

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Energy-aware register file re-partitioning for clustered VLIW architectures

2009 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2009.4796579 ◽

2009 ◽

Cited By ~ 2

Author(s):

Yingchao Zhao ◽

Chun Jason Xue ◽

Minming Li ◽

Bessie Hu

Keyword(s):

Register File ◽

Energy Aware ◽

Vliw Architectures

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Register File Energy Optimization for Snooping Based Clustered VLIW Architectures

19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07) ◽

10.1109/sbac-pad.2007.35 ◽

2007 ◽

Cited By ~ 1

Author(s):

Rahul Nagpal ◽

Y. N. Srikant

Keyword(s):

Energy Optimization ◽

Register File ◽

Vliw Architectures

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A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors ◽

10.1109/asap.2010.5541015 ◽

2010 ◽

Cited By ~ 2

Author(s):

Guillermo Paya-Vaya ◽

Javier Martin-Langerwerf ◽

Holger Blume ◽

Peter Pirsch

Keyword(s):

Instruction Scheduling ◽

Register File ◽

Vliw Architectures

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Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00127 ◽

2009 ◽

Vol 31 (1) ◽

pp. 127-132

Author(s):

Zhi-Xiong ZHOU ◽

Hu HE ◽

Xu YANG ◽

Yan-Jun ZHANG ◽

Yi-He SUN

Keyword(s):

Scheduling Algorithm ◽

Instruction Scheduling ◽

Register File

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Active-Cycle Based Register File Design for Reduced Ports and Energy

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00299 ◽

2009 ◽

Vol 31 (2) ◽

pp. 299-308 ◽

Cited By ~ 1

Author(s):

Yu-Lai ZHAO ◽

Xian-Feng LI ◽

Dong TONG ◽

Han-Xin SUN ◽

Jie CHEN ◽

...

Keyword(s):

Register File ◽

File Design

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Register/ file/ cache microarchitecture study using VHDL

Proceedings of the 24th annual international symposium on Microarchitecture - MICRO 24 ◽

10.1145/123465.123510 ◽

1991 ◽

Author(s):

Samarina Makhdoom ◽

Daniel Tabak ◽

Richard Auletta

Keyword(s):

Register File ◽

File Cache

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24.4 A 5nm [email protected] and [email protected] 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

2021 IEEE International Solid- State Circuits Conference (ISSCC) ◽

10.1109/isscc42613.2021.9366000 ◽

2021 ◽

Author(s):

Hidehiro Fujiwara ◽

Yi-Hsin Nien ◽

Chih-Yu Lin ◽

Hsien-Yu Pan ◽

Hao-Wen Hsu ◽

...

Keyword(s):

Standard Cell ◽

Register File

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