An efficient built-in self test method for robust path delay fault testing

Ioannis Voyiatzis; Antonis Paschalis; Dimitrios Nikolos; Constantin Halatsis

doi:10.1007/bf02341826

An efficient built-in self test method for robust path delay fault testing

Journal of Electronic Testing ◽

10.1007/bf02341826 ◽

1996 ◽

Vol 8 (2) ◽

pp. 219-222 ◽

Cited By ~ 20

Author(s):

Ioannis Voyiatzis ◽

Antonis Paschalis ◽

Dimitrios Nikolos ◽

Constantin Halatsis

Keyword(s):

Test Method ◽

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Self Test ◽

Path Delay Fault Testing ◽

Built In Self Test

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New advances in path delay fault testing of combinational circuits

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292301 ◽

2002 ◽

Cited By ~ 3

Author(s):

X. Xie ◽

A. Albicki

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Path delay fault testing using test points

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/606603.606604 ◽

2003 ◽

Vol 8 (1) ◽

pp. 1-10 ◽

Cited By ~ 2

Author(s):

S. Tragoudas ◽

N. Denny

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Test Points ◽

Path Delay Fault Testing

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Path delay fault testing of multiplexer-based shifters

International Journal of Electronics ◽

10.1080/00207210110058139 ◽

2001 ◽

Vol 88 (8) ◽

pp. 923-937

Author(s):

H. T. Vergos ◽

Y. Tsiatouhas ◽

Th. Haniotakis ◽

D. Nikolos ◽

M. Nicolaidis

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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A flexible path selection procedure for path delay fault testing

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) ◽

10.1109/vtest.1999.766659 ◽

2003 ◽

Cited By ~ 5

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Selection Procedure ◽

Path Selection ◽

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Path delay fault testing of Benes multistage interconnection networks

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357) ◽

10.1109/icecs.1999.813425 ◽

2003 ◽

Author(s):

H.T. Vergos ◽

M. Bellos ◽

D. Nikolos

Keyword(s):

Interconnection Networks ◽

Path Delay ◽

Fault Testing ◽

Multistage Interconnection Networks ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Tri-scan: a novel DFT technique for CMOS path delay fault testing

2004 International Conferce on Test ◽

10.1109/test.2004.1387386 ◽

2005 ◽

Cited By ~ 9

Author(s):

R. Datta ◽

Ravi Gupta ◽

A. Sebastine ◽

J.A. Abraham ◽

M. d'Abreu

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Path-Delay Fault Testing in Embedded Content Addressable Memories

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools ◽

10.1109/dsd.2010.48 ◽

2010 ◽

Cited By ~ 1

Author(s):

P. Manikandan ◽

Bjorn B. Larsen ◽

Einar J. Aas

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Content Addressable Memories ◽

Path Delay Fault Testing

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Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing

2018 IEEE East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2018.8524693 ◽

2018 ◽

Author(s):

Mahroo Zandrahimi ◽

Philippe Debaud ◽

Armand Castillejo ◽

Zaid Al-Ars

Keyword(s):

Cost Effective ◽

Voltage Scaling ◽

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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On path delay fault testing of multiplexer-based shifters

Proceedings Ninth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1999.757368 ◽

2003 ◽

Author(s):

H.T. Vergos ◽

Y. Tsiatouhas ◽

T. Haniotakis ◽

D. Nikolos ◽

M. Nicolaidis

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks

Lecture Notes in Computer Science - Dependable Computing — EDCC-3 ◽

10.1007/3-540-48254-7_19 ◽

1999 ◽

pp. 267-282 ◽

Cited By ~ 1

Author(s):

M. Bellos ◽

D. Nikolos ◽

H. T. Vergos

Keyword(s):

Interconnection Networks ◽

Path Delay ◽

Fault Testing ◽

Multistage Interconnection Networks ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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