Optical probing of ultrafast devices and integrated circuits

1996 ◽  
Vol 28 (7) ◽  
pp. 729-729 ◽  
Author(s):  
Tadao Nagatsuma
Author(s):  
R. Santos ◽  
D. D’Agostino ◽  
F. M. Soares ◽  
H. Rabbani Haghighi ◽  
M. K. Smit ◽  
...  

Author(s):  
Howard Lee Marks ◽  
Tung Ton ◽  
Jeffrey A. Block ◽  
Steven Kasapi ◽  
Chris Shaw

Abstract Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.


Author(s):  
William Lo ◽  
Kenneth Wilsher ◽  
Richard Malinsky ◽  
Nina Boiadjieva ◽  
Chun-Cheng Tsao ◽  
...  

Abstract Time-resolved photon emission (TRPE) results, obtained using a new superconducting, single-photon detector (SSPD) are reported. Detection efficiency (DE) for large area detectors has recently been improved by >100x without affecting SSPDs inherently low jitter (≈30 ps) and low dark-count rate (<30 s-1). TRPE measurements taken from a 0.13 μm geometry CMOS IC are presented. A single laser, time-differential probing scheme that is being investigated for next-generation laser voltage probing (LVP) is also discussed. This new scheme is designed to have shot-noise-limited performance, allowing signals as small as 100 parts-per-million (ppm) to be reliably measured.


Author(s):  
Wai Mun Yee ◽  
Mario Paniccia ◽  
Travis Eiles ◽  
Valluri Rao

Abstract A novel optical probing technique to measure voltage waveforms from flip-chip packaged complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) is described. This infrared (IR) laser based technique allows signal waveform acquisition and high frequency timing measurement directly from active PN junctions through the silicon backside substrate on IC’s mounted in flip-chip, stand-alone, or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug & failure analysis (FA) through-put time (TPT) as compared to backside electron-beam (E-beam) probing because of the elimination of backside trenching and probe hole generation operations.


1998 ◽  
Vol 297-298 ◽  
pp. 59-66
Author(s):  
H.G. Roskos ◽  
Tilo Pfeifer ◽  
H.-M. Heiliger ◽  
T. Löffler ◽  
H. Kurz

Author(s):  
Simon Thomas

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.


Author(s):  
L.J. Chen ◽  
Y.F. Hsieh

One measure of the maturity of a device technology is the ease and reliability of applying contact metallurgy. Compared to metal contact of silicon, the status of GaAs metallization is still at its primitive stage. With the advent of GaAs MESFET and integrated circuits, very stringent requirements were placed on their metal contacts. During the past few years, extensive researches have been conducted in the area of Au-Ge-Ni in order to lower contact resistances and improve uniformity. In this paper, we report the results of TEM study of interfacial reactions between Ni and GaAs as part of the attempt to understand the role of nickel in Au-Ge-Ni contact of GaAs.N-type, Si-doped, (001) oriented GaAs wafers, 15 mil in thickness, were grown by gradient-freeze method. Nickel thin films, 300Å in thickness, were e-gun deposited on GaAs wafers. The samples were then annealed in dry N2 in a 3-zone diffusion furnace at temperatures 200°C - 600°C for 5-180 minutes. Thin foils for TEM examinations were prepared by chemical polishing from the GaA.s side. TEM investigations were performed with JE0L- 100B and JE0L-200CX electron microscopes.


Author(s):  
E.D. Wolf

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.


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