The probability of error detection in sequential circuits using random test vectors

1991 ◽  
Vol 1 (4) ◽  
pp. 245-256 ◽  
Author(s):  
Asad A. Ismaeel ◽  
Melvin A. Breuer
Keyword(s):  
Error Detection ◽  
Sequential Circuits ◽  
Probability Of Error ◽  
Random Test ◽  
Test Vectors

scholarly journals Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 258 ◽  
Author(s):  
Abdus Hassan ◽  
Umar Afzaal ◽  
Tooba Arifeen ◽  
Jeong Lee
Keyword(s):  
Error Detection ◽  
High Probability ◽  
State Of The Art ◽  
The State ◽  
Experimental Results ◽  
Concurrent Error Detection ◽  
Selection Algorithm ◽  
Probability Of Error ◽  
Selection Scheme ◽  
Selection Strategies

Recently, concurrent error detection enabled through invariant relationships between different wires in a circuit has been proposed. Because there are many such implications in a circuit, selection strategies have been developed to select the most valuable implications for inclusion in the checker hardware such that a sufficiently high probability of error detection ( P d e t e c t i o n ) is achieved. These algorithms, however, due to their heuristic nature cannot guarantee a lossless P d e t e c t i o n . In this paper, we develop a new input-aware implication selection algorithm with the help of ATPG which minimizes loss on P d e t e c t i o n . In our algorithm, the detectability of errors for each candidate implication is carefully evaluated using error prone vectors. The evaluation results are then utilized to select the most efficient candidates for achieving optimal P d e t e c t i o n . The experimental results on 15 representative combinatorial benchmark circuits from the MCNC benchmarks suite show that the implications selected from our algorithm achieve better P d e t e c t i o n in comparison to the state of the art. The proposed method also offers better performance, up to 41.10%, in terms of the proposed impact-level metric, which is the ratio of achieved P d e t e c t i o n to the implication count.

FLOSPAT: Fault Localization by Sensitized Path Transformation

1996 ◽  
Author(s):  
M.W. Heath ◽  
W. Maly
Keyword(s):  
Boolean Functions ◽  
Fault Localization ◽  
Fault Model ◽  
Sequential Circuits ◽  
Fault Identification ◽  
Identification Algorithm ◽  
Path Tracing ◽  
Full Scan ◽  
Diagnostic Resolution ◽  
Test Vectors

Abstract This paper describes a fault identification algorithm for combinational and full-scan sequential circuits called FLOSPAT - Fault Localization by Sensitized Path Transformation [1,2]. The goal of fault identification is to localize a fault to the fewest possible gates and to determine the Boolean functions realized by those gates. Instead of choosing a fault model, FLOSPAT uses fault-independent sensitized path tracing [3] to localize functional deviations. Sensitized path transformation is used to adaptively generate test vectors which improve the diagnostic resolution. The output of FLOSPAT is used for physical defect diagnosis by cross-referencing gate-level defect dictionaries generated by the contamination-defect-fault mapper CODEF [4,5,6].

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