A Power-Efficient Processor Core for Reactive Embedded Applications

Author(s):  
Lei Yang ◽  
Morteza Biglari-Abhari ◽  
Zoran Salcic
2016 ◽  
Vol 25 (07) ◽  
pp. 1650080 ◽  
Author(s):  
Raed Bani-Hani ◽  
Khaldoon Mhaidat ◽  
Salah Harb

In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.


2015 ◽  
Vol 14 (3) ◽  
pp. 1-25 ◽  
Author(s):  
Parinaz Sayyah ◽  
Mihai T. Lazarescu ◽  
Sara Bocchio ◽  
Emad Ebeid ◽  
Gianluca Palermo ◽  
...  

2004 ◽  
Vol 28 (1) ◽  
pp. 13-25 ◽  
Author(s):  
Zoran Salcic ◽  
Partha Roop ◽  
Morteza Biglari-Abhari ◽  
Abbas Bigdeli

Author(s):  
F. Vermeulen ◽  
F. Catthoor ◽  
L. Nachtergaele ◽  
D. Verkest ◽  
H. De Man

2021 ◽  
Author(s):  
Binh Kieu-Do-Nguyen ◽  
Trong-Thuc Hoang ◽  
Cong-Kha Pham ◽  
Cuong Pham-Quoc

Sign in / Sign up

Export Citation Format

Share Document