REFLIX: a processor core with native support for control-dominated embedded applications

2004 ◽  
Vol 28 (1) ◽  
pp. 13-25 ◽  
Author(s):  
Zoran Salcic ◽  
Partha Roop ◽  
Morteza Biglari-Abhari ◽  
Abbas Bigdeli
Keyword(s):  
Processor Core ◽  
Embedded Applications

Rational Choice of Information Form Converters for Automated Systems in Construction

2020 ◽  
pp. 60-65
Keyword(s):  
Rational Choice ◽  
Construction Industry ◽  
Correct Choice ◽  
Automated System ◽  
Digital Code ◽  
Automated Control ◽  
Sigma Delta ◽  
Processor Core ◽  
Building Monitoring ◽  
High Level

In automated control systems for technical processes, the conversion of a continuous signal into a digital code and vice versa from a digital code to a continuous (analog) value is widely used. For direct type converters often used the term ADC, the reverse - DAC. The characteristics of the converters often dramatically affect the parameters of the entire automated system. The importance of the correct choice of ADCs and DACs has especially increased recently in connection with the mass introduction of microcontrollers MC. Indeed, in addition to the ADC and DAC, it is necessary to place the processor core in the microcontroller's crystal, I/O interfaces and many other elements necessary for the functioning of the MC. The use of information converters in the construction industry imposes additional requirements on converters: for example, in building monitoring systems, precision ADCs with extremely high accuracy are often required (while performance may be low), in other applications it is necessary to provide the necessary parameters at a high level of industrial interference, etc. This article explores issues related to the rational choice of ADCs and DACs, taking into account current trends in the IT field and the specifics of work in the construction industry. Sigma-Delta converters are noted as the most promising models of direct type converters.

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

scholarly journals Performance vs. hardware requirements in state-of-the-art automatic speech recognition

2021 ◽  
Vol 2021 (1) ◽  
Author(s):  
Alexandru-Lucian Georgescu ◽  
Alessandro Pappalardo ◽  
Horia Cucu ◽  
Michaela Blott
Keyword(s):  
Speech Recognition ◽  
Automatic Speech Recognition ◽  
State Of The Art ◽  
Decision Makers ◽  
Computing Power ◽  
Trade Off ◽  
Speech Features ◽  
Commercial Applications ◽  
Guided Tour ◽  
Embedded Applications

AbstractThe last decade brought significant advances in automatic speech recognition (ASR) thanks to the evolution of deep learning methods. ASR systems evolved from pipeline-based systems, that modeled hand-crafted speech features with probabilistic frameworks and generated phone posteriors, to end-to-end (E2E) systems, that translate the raw waveform directly into words using one deep neural network (DNN). The transcription accuracy greatly increased, leading to ASR technology being integrated into many commercial applications. However, few of the existing ASR technologies are suitable for integration in embedded applications, due to their hard constrains related to computing power and memory usage. This overview paper serves as a guided tour through the recent literature on speech recognition and compares the most popular ASR implementations. The comparison emphasizes the trade-off between ASR performance and hardware requirements, to further serve decision makers in choosing the system which fits best their embedded application. To the best of our knowledge, this is the first study to provide this kind of trade-off analysis for state-of-the-art ASR systems.

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