scholarly journals Ultra Power-Efficient CNN Domain Specific Accelerator with 9.3TOPS/Watt for Mobile and Embedded Applications

2018 ◽  
Author(s):  
Baohua Sun ◽  
Lin Yang ◽  
Patrick Dong ◽  
Wenhan Zhang ◽  
Jason Dong ◽  
...  
Keyword(s):  
Power Efficient ◽  
Domain Specific ◽  
Embedded Applications

Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications

2016 ◽  
Vol 25 (07) ◽  
pp. 1650080 ◽  
Author(s):  
Raed Bani-Hani ◽  
Khaldoon Mhaidat ◽  
Salah Harb
Keyword(s):  
Low Power ◽  
Area Ratio ◽  
Advanced Encryption Standard ◽  
Fpga Design ◽  
Power Efficient ◽  
Aes Algorithm ◽  
Lookup Tables ◽  
Small Footprint ◽  
Embedded Applications

In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.

scholarly journals Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications

2015 ◽  
Vol 14 (3) ◽  
pp. 1-25 ◽  
Author(s):  
Parinaz Sayyah ◽  
Mihai T. Lazarescu ◽  
Sara Bocchio ◽  
Emad Ebeid ◽  
Gianluca Palermo ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Power Efficient ◽  
Virtual Platform ◽  
Embedded Applications ◽  
Platform Based Design

Power-efficient flexible processor architecture for embedded applications

2003 ◽  
Vol 11 (3) ◽  
pp. 376-385 ◽  
Author(s):  
F. Vermeulen ◽  
F. Catthoor ◽  
L. Nachtergaele ◽  
D. Verkest ◽  
H. De Man
Keyword(s):  
Processor Architecture ◽  
Power Efficient ◽  
Embedded Applications

A Power-efficient Implementation of SHA-256 Hash Function for Embedded Applications

2021 ◽  
Author(s):  
Binh Kieu-Do-Nguyen ◽  
Trong-Thuc Hoang ◽  
Cong-Kha Pham ◽  
Cuong Pham-Quoc
Keyword(s):  
Hash Function ◽  
Efficient Implementation ◽  
Power Efficient ◽  
Embedded Applications

Design and Implementation of an Ethernet MAC IP Core for Embedded Applications

2014 ◽  
Vol 3 (3) ◽  
pp. 85
Author(s):  
Sanket Suresh Naik Dessai
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Essential Elements ◽  
Font Size ◽  
Ip Core ◽  
Real Time Control ◽  
Script Language ◽  
Power Efficient ◽  
Time Control ◽  
Embedded Applications

<!--[if gte mso 9]><xml> <o:OfficeDocumentSettings> <o:RelyOnVML /> <o:AllowPNG /> </o:OfficeDocumentSettings> </xml><![endif]--> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt;">An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications.<span style="mso-spacerun: yes;"> </span></span></p> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt; mso-bidi-font-size: 10.0pt; color: black; mso-bidi-font-weight: bold; mso-no-proof: yes;"><span style="mso-spacerun: yes;"> </span>In this paper a</span><span style="font-size: 9.0pt;"> project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.</span></p> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt;">A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. </span></p> <!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables /> <w:SnapToGridInCell /> <w:WrapTextWithPunct /> <w:UseAsianBreakRules /> <w:UseFELayout /> </w:Compatibility> </w:WordDocument> </xml><![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-fareast-font-family:"Times New Roman";} </style> <![endif]-->

Scientific Problem Solving in a Virtual Laboratory: A Comparison Between Individuals and Pairs

2008 ◽  
Vol 67 (2) ◽  
pp. 71-83 ◽  
Author(s):  
Yolanda A. Métrailler ◽  
Ester Reijnen ◽  
Cornelia Kneser ◽  
Klaus Opwis
Keyword(s):  
Visual Search ◽  
Problem Solving ◽  
Process Data ◽  
Scientific Problem ◽  
Domain Specific ◽  
Scientific Problem Solving ◽  
Before And After ◽  
Verbal Data ◽  
Psychological Knowledge ◽  
Problem Solving Task

This study compared individuals with pairs in a scientific problem-solving task. Participants interacted with a virtual psychological laboratory called Virtue to reason about a visual search theory. To this end, they created hypotheses, designed experiments, and analyzed and interpreted the results of their experiments in order to discover which of five possible factors affected the visual search process. Before and after their interaction with Virtue, participants took a test measuring theoretical and methodological knowledge. In addition, process data reflecting participants’ experimental activities and verbal data were collected. The results showed a significant but equal increase in knowledge for both groups. We found differences between individuals and pairs in the evaluation of hypotheses in the process data, and in descriptive and explanatory statements in the verbal data. Interacting with Virtue helped all students improve their domain-specific and domain-general psychological knowledge.

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