Reduction of the thermal budget of AlGaN/GaN heterostructures grown on silicon: A step towards monolithic integration of GaN-HEMTs with CMOS

2015 ◽  
Vol 212 (5) ◽  
pp. 1145-1152 ◽  
Author(s):  
Rémi Comyn ◽  
Yvon Cordier ◽  
Vincent Aimez ◽  
Hassan Maher
Keyword(s):  
Monolithic Integration ◽  
Thermal Budget ◽  
Gan Hemts

Low Thermal Budget Monolithic Integration of Evanescent-Coupled Ge-on-SOI Photodetector on Si CMOS Platform

2010 ◽  
Vol 16 (1) ◽  
pp. 106-113 ◽  
Author(s):  
Kah-Wee Ang ◽  
Tsung-Yang Liow ◽  
Ming-Bin Yu ◽  
Qing Fang ◽  
Junfeng Song ◽  
...  
Keyword(s):  
Monolithic Integration ◽  
Thermal Budget ◽  
Low Thermal Budget

scholarly journals 200 V Enhancement-Mode p-GaN HEMTs Fabricated on 200 mm GaN-on-SOI With Trench Isolation for Monolithic Integration

2017 ◽  
Vol 38 (7) ◽  
pp. 918-921 ◽  
Author(s):  
Xiangdong Li ◽  
Marleen Van Hove ◽  
Ming Zhao ◽  
Karen Geens ◽  
Vesa-Pekka Lempinen ◽  
...  
Keyword(s):  
Monolithic Integration ◽  
Enhancement Mode ◽  
Trench Isolation ◽  
Gan Hemts

Development of technological building blocks for the monolithic integration of ammonia-MBE-grown GaN-HEMTs with silicon CMOS

2016 ◽  
Vol 213 (4) ◽  
pp. 917-924 ◽  
Author(s):  
Rémi Comyn ◽  
Yvon Cordier ◽  
Sébastien Chenot ◽  
Abdelatif Jaouad ◽  
Hassan Maher ◽  
...  
Keyword(s):  
Building Blocks ◽  
Monolithic Integration ◽  
Gan Hemts ◽  
Silicon Cmos

scholarly journals Suppression of the Backgating Effect of Enhancement-Mode p-GaN HEMTs on 200-mm GaN-on-SOI for Monolithic Integration

2018 ◽  
Vol 39 (7) ◽  
pp. 999-1002 ◽  
Author(s):  
Xiangdong Li ◽  
Marleen Van Hove ◽  
Ming Zhao ◽  
Karen Geens ◽  
Weiming Guo ◽  
...  
Keyword(s):  
Monolithic Integration ◽  
Enhancement Mode ◽  
Gan Hemts

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

2015 ◽  
Vol 113 ◽  
pp. 2-8 ◽  
Author(s):  
C. Fenouillet-Beranger ◽  
B. Previtali ◽  
P. Batude ◽  
F. Nemouchi ◽  
M. Cassé ◽  
...  
Keyword(s):  
Monolithic Integration ◽  
Thermal Budget

A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee
Keyword(s):  
Process Condition ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Core Shell ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
New Process ◽  
Comparable Performance ◽  
Higher Temperature ◽  
Film Annealing

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

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