Structural, nonlinear electrical characteristics, and stability against DC ‐accelerated aging stress behavior of Er‐doped 20 nm ZnO – Bi 2 O 3 – Mn 2 O 3 ‐based varistors

2021 ◽  
Author(s):  
Rabab Khalid Sendi
Keyword(s):  
Accelerated Aging ◽  
Electrical Characteristics ◽  
Stress Behavior ◽  
Er Doped ◽  
20 Nm

Direct observations of compositional changes of sub-20-nm Er-doped phase-separated nanoparticles in optical fibers (Conference Presentation)

2019 ◽  
Author(s):  
Wilfried Blanc ◽  
Isabelle Martin ◽  
Hugues François Saint-Cyr ◽  
Xavier Bidault ◽  
Stéphane Chaussedent ◽  
...  
Keyword(s):  
Optical Fibers ◽  
Direct Observations ◽  
Compositional Changes ◽  
Er Doped ◽  
20 Nm

THERMAL STRESS BEHAVIOR IN NANO-SIZE THIN ALUMINUM FILMS

2006 ◽  
Vol 20 (25n27) ◽  
pp. 4691-4696 ◽  
Author(s):  
TAKAO HANABUSA ◽  
KAZUYA KUSAKA ◽  
SHOSO SHINGUBARA ◽  
OSAMI SAKATA
Keyword(s):  
Thin Films ◽  
Thermal Stress ◽  
Synchrotron Radiation ◽  
Thermal Stresses ◽  
In Situ Observation ◽  
Aluminum Films ◽  
Stress Behavior ◽  
Thin Aluminum ◽  
20 Nm ◽  
Nano Size

In-situ observation of thermal stresses in thin films deposited on a silicon substrate was made by synchrotron radiation. Specimens prepared in this experiment were nano-size thin aluminum films with SiO 2 passivation. The thickness of the films was 10 nm, 20 nm and 50 nm. Synchrotron radiation revealed the diffraction intensities for these thin films and make possible to measure stresses in nano-size thin films. Residual stresses in the as-deposited state were tensile. Compressive stresses were developed in a heating cycle up to 300°C and tensile stresses were developed in a cooling cycle. The thermal stresses in the 50 nm film showed linear behavior in the first heating stage from room temperature to 250°C followed by no change in the stress at 300°C, however, linearly behaved in the second cycle. On the other hand, the thermal stresses in 20 nm and 10 nm films almost linearly behaved without any hysteresis in increasing and decreasing temperature cycles. The mechanism of thermal stress behavior in thin films can be explained by strengthening of the nano-size thin films due to inhibition of dislocation source and dislocation motion.

scholarly journals Electrical characteristics of Er doped BaTiO3 ceramics

2017 ◽  
Vol 49 (2) ◽  
pp. 129-137 ◽  
Author(s):  
Vesna Paunovic ◽  
Vojislav Mitic ◽  
Milos Djordjevic ◽  
Milos Marjanovic ◽  
Ljubisa Kocic
Keyword(s):  
Electrical Resistivity ◽  
Temperature Response ◽  
Sem Analysis ◽  
Electrical Characteristics ◽  
Conventional Solid State Reaction ◽  
Homogeneous Microstructure ◽  
Temperature Range ◽  
Grain Sizes ◽  
Air Atmosphere ◽  
Er Doped

In this study, the electrical resistivity (?) and PTC effect of Er doped BaTiO3 ceramics are investigated. The concentrations of Er2O3 in the doped samples vary from 0.01 to 1.0 at% Er. The samples are prepared by the conventional solid state reaction, and sintered at 1320? and 1350?C in air atmosphere for 4 hours. The SEM analysis shows that all of measured samples are characterized by polygonal grains. The uniform and homogeneous microstructure with grain sizes from 20 to 45?m is the main characteristic of the low doped samples (0.01 and 0.1 at% Er). For the samples doped with the higher dopant concentration (0.5 and 1.0 at%) the average grains sizes have been ranged from 5 to 10 ?m. The electrical resistivity is measured in the temperature range from 25?C to 170?C, at frequencies 1 kHz, 10 kHz and 100 kHz. The electrical resistivity values, measured at frequency of 1 kHz and room temperature, have been ranged from 1.62?104 ?cm to 4.24?104 ?cm, for samples sintered at 1320?C and from 1.43?104 ?cm to 1.94?104 ?cm, for samples sintered at 1350?C. A nearly flat and stable electrical resistivity-temperature response is characteristic for all samples at the temperature range from 25?C to 120?C. Above this temperature, the electrical resistivity increases rapidly. At 170?C the value of electrical resistivity is ranged 9.84?104 ?cm -1.62?105 ?cm, for Tsin=1320?C, and 6.11?104 ?cm 1.32?105 ?cm, for Tsin=1350?C. The electrical resistivity decreases with concentration increment up to 0.5 at%, while above 0.5 at% it increases. Also, with increasing frequency, ? decreases for a few orders of magnitude.

scholarly journals Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

2021 ◽  
Author(s):  
Aruna Kumari Neelam ◽  
Prithvi P
Keyword(s):  
Temperature Compensation ◽  
High Performance ◽  
Field Effect Transistor ◽  
Performance Metrics ◽  
Electrical Characteristics ◽  
Transfer Characteristics ◽  
Wide Range ◽  
Effect Transistor ◽  
20 Nm ◽  
The Impact

Abstract Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs for different geometrical configurations of the NSFET. In this script, DC performance of 3D GAA NSFET is analyzed by varying the width, thickness of the device. Moreover, the gate length is scaled from 20 nm to 5 nm to check for the device suitability in logic applications. The thickness and width of each nanosheet are varied in the range of 5 to 9 nm, and 10 to 50 nm respectively to analyse the performance dependency on the geometry of the device. The impact of geometry of NSFET on various DC performance metrics like transfer characteristics, sub-threshold swing (SS), on current (ION), off current (IOFF), switching ratio (ION/IOFF), threshold voltage (Vth) and drain induced barrier lowering (DIBL) are studied. On top of that, the device’s electrical characteristics are analyzed for a wide range of temperatures from -43oC to 127oC to identify the temperature compensation point and is observed at VGS = 0.55 V and ID = 3.86 × 10−6 A. Furthermore, the important process parameter, work function variations on transfer characteristics of the device is analyzed. Moreover, the analyses tell that, for sub -7 nm, the NSFET is a potential device for high performance and good logic applications.

scholarly journals Study of hyaluronic acid flexibility by electric birefringence

1983 ◽  
Vol 213 (3) ◽  
pp. 671-677 ◽  
Author(s):  
H H Trimm ◽  
B R Jennings
Keyword(s):  
Hyaluronic Acid ◽  
Molecular Conformation ◽  
Persistence Length ◽  
Relaxation Times ◽  
Electrical Characteristics ◽  
Random Coils ◽  
Electric Birefringence ◽  
Dilute Aqueous Solution ◽  
Transient Electric Birefringence ◽  
20 Nm

Transient-electric-birefringence experiments were conducted on four samples of hyaluronic acid over the molecular-mass (M) range 5 X 10(4)-4 X 10(6) in dilute aqueous solution. The geometrical, optical and electrical characteristics were monitored via the rotary relaxation times, optical-polarizability antisotropies and electrical polarizabilities respectively. Each indicates the molecular conformation to be consistent with some degree of rigidity at low M but that this does not persist at high M. The molecules do not become true random coils, but are best characterized in terms of a persistence length of 20 nm or 20 disaccharide units.

scholarly journals Incorporation of Phosphorus Impurities in a Silicon Nanowire Transistor with a Diameter of 5 nm

Micromachines ◽  
2019 ◽  
Vol 10 (2) ◽  
pp. 127 ◽  
Author(s):  
Yanfeng Jiang ◽  
Wenjie Wang ◽  
Zirui Wang ◽  
Jian-Ping Wang
Keyword(s):  
Doping Concentration ◽  
Silicon Nanowire ◽  
Nanometer Scale ◽  
Inhomogeneous Distribution ◽  
Electrical Characteristics ◽  
Phosphorus Doping ◽  
Impurity Segregation ◽  
20 Nm ◽  
Positive Effect ◽  
Incorporation Method

Silicon nanowire (SiNW) is always accompanied by severe impurity segregation and inhomogeneous distribution, which deteriorates the SiNWs electrical characteristics. In this paper, a method for phosphorus doping incorporation in SiNW was proposed using plasma. It showed that this method had a positive effect on the doping concentration of the wires with a diameter ranging from 5 nm to 20 nm. Moreover, an SiNW transistor was assembled based on the nanowire with a 5 nm diameter. The device’s ION/IOFF ratio reached 104. The proposed incorporation method could be helpful to improve the effect of the dopants in the silicon nanowire at a nanometer scale.

Origins of Residual Stress in Mo and Ta Films: the Role of Impurities, Microstructural Evolution, and Phase Transformations

1996 ◽  
Vol 436 ◽  
Author(s):  
L. J. Parfitt ◽  
O. P. Karpenko ◽  
Z. U. Rek ◽  
S. M. Yalisove ◽  
J. C. Bilello
Keyword(s):  
Residual Stress ◽  
Film Thickness ◽  
Phase Transformations ◽  
Compressive Stress ◽  
Native Oxide ◽  
Si Substrates ◽  
Stress Behavior ◽  
Sputter Deposited ◽  
Substrate Surfaces ◽  
20 Nm

AbstractBoth the sign and magnitude of residual stress can vary with the thickness of sputter deposited films. The origins of this behavior are not well understood. In this work, we consider the correlation between the residual stress behavior and the depth dependence of impurities in thin (2.5 nm - 150 nm) sputtered Mo and Ta films. We also consider the effects of phase transformations and microstructural changes on the stress behavior. Films were deposited onto Si substrates with native oxide. The residual stress observed in the Mo films varied from highly compressive at 2.5 nm film thickness to ∼ 0 ˜ 10 nm thickness. Ta films also exhibited a high compressive stress, which relaxed from highly compressive to tensile between 10 nm and 50 nm film thickness. Impurities in the films may originate from the sputtering targets, the background gases, and the substrate surfaces. Auger Electron Spectroscopy (AES) results showed the presence of O and C contamination near the film/Si interface; these impurities contributed to the compressive stresses in the thinner films. As anticipated, both Mo and Ta films exhibited grain growth as a function of film thickness, which may have contributed to the relaxation in the compressive stress. The Mo films were entirely bcc. The Ta films showed a transformation from the amorphous phase to the β crystalline phase between 2.5 nm and 20 nm film thickness, which contributed to the relaxation in stress observed in that thickness regime.

Titanium silicide and titanium nitride formation by titanium-ion implantation for MOS LSI applications

1991 ◽  
Vol 6 (6) ◽  
pp. 1238-1247 ◽  
Author(s):  
Yasuhisa Omura ◽  
Hiroshi Inokawa ◽  
Katsutoshi Izumi
Keyword(s):  
Ion Implantation ◽  
Titanium Silicide ◽  
Double Layers ◽  
Implantation Technique ◽  
Electrical Characteristics ◽  
Mos Capacitors ◽  
Silicide Layer ◽  
Nitride Formation ◽  
Device Applications ◽  
20 Nm

A 70-nm-thick, 19-μΩ · cm TiSi2 layer is formed using a Ti-ion implantation technique. TiN/TiSi2 double layers, whose surface morphology is superior to that obtained with conventional deposition and reaction techniques, can also be simultaneously formed by Ti-ion implantation into monocrystalline Si screened with the Si3N4 film. Discrete pn-junction diodes with a shallow TiSi2 layer and Ti-polycide-gate MOS capacitors are fabricated to determine the influences of Ti-ion implantation on electrical characteristics. The leakage current of the B-doped p+n junction and As/P-doped n+p junction with Ti-ion implanted silicide layer is low enough for device applications. Silicide formation on the gate polycrystalline-Si does not affect the breakdown electric field strength of a 20-nm-thick gate oxide. MOS capacitors showed normal C-V characteristics.

Sign in / Sign up

Export Citation Format

Share Document