An intermodulation distortion estimation method for linear CMOS circuits

2021 ◽  
Author(s):  
Dimitrios Baxevanakis ◽  
Vassilis Alimisis ◽  
Paul P. Sotiriadis
Keyword(s):  
Estimation Method ◽  
Intermodulation Distortion ◽  
Cmos Circuits ◽  
Distortion Estimation

Fine Virtual View Distortion Estimation Method for Depth Map Coding

2018 ◽  
Vol 25 (3) ◽  
pp. 417-421 ◽  
Author(s):  
Ziqi Zheng ◽  
Junyan Huo ◽  
Bingbing Li ◽  
Hui Yuan
Keyword(s):  
Estimation Method ◽  
Depth Map ◽  
Virtual View ◽  
Distortion Estimation

POWER ANALYSIS OF VLSI INTERCONNECT WITH RLC TREE MODELS AND MODEL REDUCTION

2006 ◽  
Vol 15 (03) ◽  
pp. 399-408 ◽  
Author(s):  
YOUNGSOO SHIN ◽  
JUNGHYUP LEE
Keyword(s):  
Model Reduction ◽  
Power Analysis ◽  
Estimation Method ◽  
Power Estimation ◽  
Reduction Technique ◽  
Cmos Circuits ◽  
Tree Models ◽  
Capacitance Model ◽  
Model Reduction Technique ◽  
Wire Resistance

The lumped capacitance model, which ignores the existence of wire resistance, has been traditionally used to estimate the charging and discharging power consumption of CMOS circuits. We show that this model is not correct by pointing out that MOSFETs consume only part of the energy supplied by the source. During this study, it was revealed that about 20% of the power is consumed in the wire resistance of the buffered global interconnect, when the interconnect is modeled with RC tree networks. The percentage goes up to 30 when RLC model is used indicating the importance of inductance in interconnect model for power estimation. For RLC networks, we propose a compact yet very accurate power estimation method based on a model reduction technique.

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