FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

2020 ◽  
Vol 48 (8) ◽  
pp. 1304-1318
Author(s):  
Kesavan Subannan Palanisamy ◽  
Rajeswari Ramachandran
Keyword(s):  
Reversible Logic ◽  
Power Gating ◽  
Power Efficient ◽  
Low Leakage ◽  
Area Efficient

Design of a Power Efficient ALU Using Reversible Logic Gates

2018 ◽  
pp. 469-479
Author(s):  
B. Abdul Rahim ◽  
B. Dhananjaya ◽  
S. Fahimuddin ◽  
N. Bala Dastagiri
Keyword(s):  
Logic Gates ◽  
Reversible Logic ◽  
Power Efficient ◽  
Reversible Logic Gates

scholarly journals A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

2013 ◽  
Vol 73 (14) ◽  
pp. 8-14
Author(s):  
Satish Sharma ◽  
Shyam Babu Singh ◽  
Shyam Akashe
Keyword(s):  
Reversible Logic ◽  
Power Efficient

New Low-leakage Flip-flops with Power-gating Scheme for Ultra-low Power Systems

2011 ◽  
Vol 10 (11) ◽  
pp. 2161-2167 ◽  
Author(s):  
Jianping Hu ◽  
Xiaoying Yu ◽  
Jindan Chen
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Power Gating ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Gating Scheme

scholarly journals A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Xiaohui Fan ◽  
Yangbo Wu ◽  
Hengfeng Dong ◽  
Jianping Hu
Keyword(s):  
Vlsi Design ◽  
Leakage Power ◽  
Total Power ◽  
Sleep Mode ◽  
Power Gating ◽  
Data Retention ◽  
Flip Flop ◽  
Low Leakage ◽  
Area Overhead ◽  
Technology Process

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper. Two high-Vthtransistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

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