Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell

2016 ◽  
Author(s):  
A. Venkatareddy ◽  
R. Sithara ◽  
M.H. Vasantha
Keyword(s):  
Leakage Power ◽  
Low Leakage ◽  
Sram Cell ◽  
Area Efficient

Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell

2018 ◽  
Author(s):  
Dhavala Shashidhar ◽  
Vivek Sharma ◽  
G.R. Prashanth ◽  
Y.B. Nithin Kumar ◽  
M.H. Vasantha
Keyword(s):  
Leakage Power ◽  
Power Efficient ◽  
Low Leakage ◽  
Sram Cell

Design of Low Leakage 9T SRAM Cell with -Low Power Devices

2021 ◽  
pp. 2250027
Author(s):  
Harekrishna Kumar ◽  
V.K Tomar
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Leakage Power ◽  
Access Time ◽  
Threshold Region ◽  
Large Area ◽  
Transmission Gate ◽  
Low Leakage ◽  
Sram Cell

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by [Formula: see text] and [Formula: see text] as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text] and [Formula: see text] as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has [Formula: see text] and [Formula: see text] higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ([Formula: see text]) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies [Formula: see text] large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3[Formula: see text]V supply voltage.

scholarly journals Low leakage SRAM cell for ULP applications

2018 ◽  
Vol 7 (4) ◽  
pp. 2521
Author(s):  
Tripti Tripathi ◽  
D. S. Chauhan ◽  
S. K. Singh
Keyword(s):  
Low Power ◽  
Electronic Devices ◽  
Leakage Power ◽  
Power Devices ◽  
Low Leakage ◽  
Sram Cell ◽  
Design Cycle ◽  
Mode Of Operation ◽  
Power Leakage ◽  
Standby Mode

Leakage power is becoming a major concern in battery operated and hand held devices. With the ever reducing size of electronic devices and the use of memory in most of them, the need for low power devices is vastly increasing. These devices are either in active or standby mode of operation. Leakage power in standby mode of operation is of major concern and various methods to minimize it have been proposed at various stages of design cycle. This paper proposes fingering technique that can be used in 6T SRAM cell to reduce leakage power. Leakage power is calculated for 6T SRAM cell designed using two fingers in access transistors and on comparison with conventional 6T SRAM cell, significant reduction in leakage current is obtained. The layout has been designed in UMC 55nm technology using Cadence Virtuoso tool and it has been shown that the leakage power and delay can be reduced.  

Design and Characterization of Area-Efficient Trench Termination for 4H-SiC Devices

2019 ◽  
Vol 7 (3) ◽  
pp. 1519-1526 ◽  
Author(s):  
Hengyu Wang ◽  
Jue Wang ◽  
Li Liu ◽  
Na Ren ◽  
Jiupeng Wu ◽  
...  
Keyword(s):  
Area Efficient

scholarly journals Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1718
Author(s):  
Neha Gupta ◽  
Ambika Prasad Shah ◽  
Sajid Khan ◽  
Santosh Kumar Vishvakarma ◽  
Michael Waltl ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Functional Improvement ◽  
Scaling Technique ◽  
Iot Applications ◽  
Sram Cell ◽  
Improved Stability ◽  
Supply Voltage Scaling ◽  
Power Delay Product

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

Sign in / Sign up

Export Citation Format

Share Document