scholarly journals Thermal design power and vectorized instructions behavior

2021 ◽  
Author(s):  
Amina Guermouche ◽  
Anne‐Cécile Orgerie
Keyword(s):  
Thermal Design ◽  
Design Power

scholarly journals Towards a Thermal Moore’s Law

2005 ◽  
Author(s):  
Shankar Krishnan ◽  
Suresh V. Garimella ◽  
Greg M. Chrysler ◽  
Ravi V. Mahajan
Keyword(s):  
Heat Sink ◽  
High Efficiency ◽  
Thermal Design ◽  
Air Cooling ◽  
Thermoelectric Coolers ◽  
Moore’S Law ◽  
Moore's Law ◽  
The Impact ◽  
Power Densities ◽  
Design Power

The thermal design power trends and power densities for present and future microprocessors are investigated. The trends are derived based on Moore’s law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of the projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of an air-cooling limit consistent with Moore’s law is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.

Improvement in Server Compute Performance Using Advanced Air Cooled Thermal Solutions

2017 ◽  
Author(s):  
Devdatta Kulkarni ◽  
Sandeep Ahuja ◽  
Sanjoy Saha
Keyword(s):  
Form Factor ◽  
Boundary Conditions ◽  
High Performance ◽  
Thermal Design ◽  
Air Cooling ◽  
Liquid Cooling ◽  
Increasing Demand ◽  
Performance Computing ◽  
Design Power

Continuously increasing demand for higher compute performance is pushing for improved advanced thermal solutions. In high performance computing (HPC) area, most of the end users deploy some sort of direct or indirect liquid cooling thermal solutions. But for the users who have air cooled data centers and air cooled thermal solutions are challenged to cool next generation higher Thermal Design Power (TDP) processors in the same platform form factor without changing environmental boundary conditions. This paper presents several different advanced air cooled technologies developed to cool high TDP processors in the same form factor and within the same boundary conditions of current generation processor. Comparison of thermal performance using different cooling technologies such as Liquid Assist Air Cooling (LAAC) and Loop Heat Pipe (LHP) are presented in this paper. A case study of Intel’s Knights Landing (KNL) processor is presented to show case the increase in compute performance due to different advanced air cooling technologies.

scholarly journals Simulation of the thermal control system of nanosatellite using the loop heat pipes under the orbital flight conditions

2021 ◽  
Vol 22 (1) ◽  
pp. 23-35
Author(s):  
Yu Wang ◽  
Oleg V. Denisov ◽  
Liliana V. Denisova
Keyword(s):  
Control System ◽  
Thermal Regime ◽  
Thermal Power ◽  
Heat Removal ◽  
Heat Pipes ◽  
Thermal Control ◽  
Thermal Design ◽  
Loop Heat Pipes ◽  
Thermal Control System ◽  
Design Power

One of the key problems in the development of nanosatellites is to provide a given temperature range for the operation of the on-board computer. The constantly increasing information load leads to the need to use more advanced processors with high thermal design power (TDP). The indicated thermal regime of processors can be achieved using remote heat removal systems - miniature loop heat pipes. Using a model of nanosatellite as an example, a thermal control system with miniature loop heat pipes is designed. The simulation was carried out in the Siemens NX program in the elliptical and geostationary orbits of the Earth. The cooling schemes of the processor with a thermal power of 15 W using one and two loop heat pipes are considered. Calculations showed that the use of loop heat pipes can reduce the processor temperature to acceptable values. The anisotropy of the thermal conductivity coefficient in the reinforcement plane of the composite material of the nanosatellite case can have a significant effect on the temperature of the processor. This opens up prospects for the use of anisotropic composite materials to ensure the thermal regime of the nanosatellite.

scholarly journals Power Management to Meet Thermal Safe Power in Fault-Tolerant Embedded Systems

2021 ◽  
Author(s):  
Mohsen Ansari ◽  
Sina Yari-Karin ◽  
Sepideh Safari ◽  
Alireza Ejlali
Keyword(s):  
Embedded Systems ◽  
Power Management ◽  
Thermal Management ◽  
Fault Tolerant ◽  
Thermal Design ◽  
Time Constraints ◽  
Power Constraint ◽  
Dynamic Thermal Management ◽  
The Core ◽  
Design Power

Thermal Design Power (TDP) as the chip-level power constraint for a specific chip has been exploited in fault-tolerant embedded systems. TDP, as the chip-level power constraint of the system, could be either pessimistic or thermally unsafe. Employing TDP as a pessimistic constraint can increase the rate of missing real-time constraints because of triggering Dynamic Thermal Management (DTM) more frequently. If TDP as a chip-level power constraint is not a pessimistic constraint, TDP can be thermally unsafe and can lead to thermal violations. Employing Thermal Safe Power (TSP) as the core-level power constraint, which is defined as a function of the number of simultaneously operating cores, can result in improving the efficiency and the schedulability. This comment improves the efficiency and the schedulability rate of one of the proposed methods in the literature by employing TSP.

A Simple Model for Transient Thermal Behavior of Integrated Circuit Package Systems for Use in Determining a Thermal Design Power

2009 ◽  
Author(s):  
Julia C. Huang ◽  
Niyati Pise ◽  
Deepak Ganapathy ◽  
Shushanth Prabhu ◽  
Ethan J. Warner
Keyword(s):  
Integrated Circuit ◽  
Thermal Characteristics ◽  
Thermal Response ◽  
Thermal Design ◽  
Clear Understanding ◽  
Power Performance ◽  
Correlation Models ◽  
Electrical Analogy ◽  
Transient Thermal ◽  
Design Power

The ever increasing power dissipation requirements of electronic components and the need to provide reliable, cost-effective thermal solutions requires the thermal engineer to accurately understand the component’s thermal design power (TDP). The TDP is impacted not only by the power-performance characteristics of the component architecture, but also by the inherent thermal characteristics of the cooling solution. A suitable TDP definition thus requires a clear understanding of the transient thermal response (resistance and capacitance) of the cooling solution. In this paper, a simple electrical analogy impedance network model that resembles the component with cooling solution is developed. Correlation models to predict the resistance and capacitance for this impedance network are built based on easily available parameters such as heat sink mass, surface area, specific heat etc. The accuracies of these models are validated experimentally with data collected on a PCB with several different thermal solutions. Development of these correlation models eliminates the need for complex time consuming transient experiments to characterize the system thermal characteristics like capacitance, which allows faster, more realistic TDP definitions and ability to analyze multiple thermal designs quickly and accurately.

Forced-Convection Boiling Characteristics Based on Mass and Energy Conservation

2007 ◽  
Author(s):  
Keisuke Horiuchi ◽  
Shigeo Ohashi
Keyword(s):  
Energy Conservation ◽  
Thermal Resistance ◽  
Forced Convection ◽  
Flow Rate ◽  
Thermal Design ◽  
Two Phase ◽  
Working Fluids ◽  
Optimum Flow Rate ◽  
Design Power ◽  
Optimum Flow

This paper presents an experimental study and theoretical interpretation of two-phase flow in a closed loop. The objective of this work is to find the optimum flow rate with respect to the thermal design power (amount of heat to be rejected). We assume that forced-convection boiling characteristics are explained based on mass and energy conservation, and claim that our proposed coefficient (C ≡ QL / Q : a ratio of amount of evaporated liquid to the flow rate) indicates the optimum flow rate for wide variation of evaporator-shapes and working fluids. In order to verify our model, we have measured the thermal resistance of evaporator with respect to heater input power for various flow rates. Hydrofluoro ether (HFE) and Fluorinert™ refrigerants were used as the working fluid in the experiment. Here flow rate of 40∼120ml/min and thermal design power of 50∼200W were controlled by the pump and by the heater, respectively. We observed that the coefficient resulted in the optimum flow rate is almost the same regardless of working fluids and evaporator shapes. The data which indicates the optimum flow rate were quite well reproduced by our proposed theory when the value of this coefficient is C ≈ 0.7∼0.95. For the demonstration, we designed the assembled-type two-phase cooling module with the optimum flow rate based on our model, and we observed that the evaporator had a relatively small thermal resistance of 0.1K/W.

Peak Power Management to Meet Thermal Design Power in Fault-Tolerant Embedded Systems

2019 ◽  
Vol 30 (1) ◽  
pp. 161-173 ◽  
Author(s):  
Mohsen Ansari ◽  
Sepideh Safari ◽  
Amir Yeganeh-Khaksar ◽  
Mohammad Salehi ◽  
Alireza Ejlali
Keyword(s):  
Embedded Systems ◽  
Power Management ◽  
Peak Power ◽  
Fault Tolerant ◽  
Thermal Design ◽  
Design Power

scholarly journals The Trend of Different Parameters for Designing Integrated Circuits from 1973 to 2019 and Linked to Moore's Law

2020 ◽  
pp. 16-23 ◽  
Keyword(s):  
Integrated Circuits ◽  
Thermal Design ◽  
Microsoft Excel ◽  
Feature Size ◽  
Moore’S Law ◽  
Moore's Law ◽  
Strong Relation ◽  
And Storage ◽  
Design Power

The number of transistors per chip, feature sizes, frequencies, transistor densities, number of cores, thermal design powers, die areas, and storage capacities of Integrated Circuits (ICs) used for different processing units and memories were collected from various websites from 1973 to 2019 and plotted against year of introduction of ICs in semi-log paper to find the trend with R-squared (R2) value using Microsoft Excel. The R2 values of the trend lines for the above parameters were over 0.922 which indicated that more than 92% of data satisfied the fitting lines except for thermal design power (R2 = 0.7) and die area (R2 = 0.4 to 0.6). It was observed that the growths of transistor counts, transistor densities, frequencies, and thermal design powers for different processing units were growing exponentially and doubled every 16.8 to 24 months from 1973 to 2019 except the growth of thermal design powers (TDP) and frequencies of ICs which were increased up to 2003. After that, the growth of TDP and frequencies are nearly linear up to the present day. The growth of the above parameters for ICs of different memories was a little faster, it was doubled every 14 to 16 months. The feature sizes shrunk 2 times every 18 months. A strong relation was found between feature sizes and transistor densities (R2 = 0.9) and observed that one fold of feature size decreased for the increasing of 2-3 folds of transistor densities. It was observed that different parameters for ICs designing from 1973 to 2019 kept pace with Moore's law. It may be concluded that the decrease of feature size, increasing of transistor count and transistor density in ICs design will follow Moore's law for some more years with the limitation of frequency and power of ICs.

Sign in / Sign up

Export Citation Format

Share Document