Instruction scheduling for a clustered VLIW processor with a word-interleaved cache

2006 ◽  
Vol 18 (11) ◽  
pp. 1391-1411
Author(s):  
Enric Gibert ◽  
Jesús Sánchez ◽  
Antonio González
Keyword(s):  
Instruction Scheduling ◽  
Vliw Processor

Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

2009 ◽  
Vol 31 (1) ◽  
pp. 127-132
Author(s):  
Zhi-Xiong ZHOU ◽  
Hu HE ◽  
Xu YANG ◽  
Yan-Jun ZHANG ◽  
Yi-He SUN
Keyword(s):  
Scheduling Algorithm ◽  
Instruction Scheduling ◽  
Register File

Integrating register allocation and instruction scheduling for RISCs

1991 ◽  
Vol 26 (4) ◽  
pp. 122-131 ◽  
Author(s):  
David G. Bradlee ◽  
Susan J. Eggers ◽  
Robert R. Henry
Keyword(s):  
Register Allocation ◽  
Instruction Scheduling

The Marion system for retargetable instruction scheduling

1991 ◽  
Vol 26 (6) ◽  
pp. 229-240 ◽  
Author(s):  
David G. Bradlee ◽  
Robert R. Henry ◽  
Susan J. Eggers
Keyword(s):  
Instruction Scheduling
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