A Poly‐Crystalline Silicon Nanowire Transistor with Independently Controlled Double‐Gate for Physically Unclonable Function by Multi‐States and Self‐Destruction

2021 ◽  
pp. 2000989
Author(s):  
Ji‐Man Yu ◽  
Gyeong‐Jun Yun ◽  
Moon‐Seok Kim ◽  
Joon‐Kyu Han ◽  
Da‐Jin Kim ◽  
...  
Keyword(s):  
Crystalline Silicon ◽  
Silicon Nanowire ◽  
Double Gate ◽  
Nanowire Transistor

scholarly journals Fabrication of p-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor by Atomic Force Microscopy Nanolithography

Nano Hybrids ◽  
2013 ◽  
Vol 3 ◽  
pp. 93-113 ◽  
Author(s):  
Arash Dehzangi ◽  
Farhad Larki ◽  
Jumiah Hassan ◽  
Sabar D. Hutagalung ◽  
Elias B. Saion ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
Gate Voltage ◽  
Potassium Hydroxide ◽  
Silicon Nanowire ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Force Microscopy ◽  
Atomic Force ◽  
Nanowire Transistor ◽  
P Type

In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (105 cm-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode.

A Drain Current and Transconductance Analytical Model for Symmetric Double Gate Junctionless FENT

2020 ◽  
Vol 65 ◽  
pp. 39-50
Author(s):  
N. Bora ◽  
N. Deka ◽  
R. Subadar
Keyword(s):  
Analytical Model ◽  
Field Effect ◽  
Drain Current ◽  
Double Gate ◽  
Double Integral ◽  
Electrical Parameters ◽  
Continuity Equations ◽  
Nanowire Transistor ◽  
Drain Conductance ◽  
Tcad Simulations

This paper presents an analytical model of various electrical parameters for an ultra thin symmetric double gate (SDG) junctionless field effect nanowire transistor (JLFENT). The model works for all the regions of operation of the nanowire transistor without using any fitting parameter. The surface potential is derived based on the solutions of Poisson’s and current continuity equations by using appropriate boundary conditions. The Pao–Sah double integral was used to obtain the drain current, transconductance and drain conductance. The results obtained from analytical model are validated by comparing with GENIUS 3D TCAD simulations. The simplicity of the model makes it appropriate to be a SPICE compatible model.

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