Gate-Voltage Control of Optically- Induced Charges and Memory Effects in Polymer Field-Effect Transistors

2004 ◽  
Vol 16 (23-24) ◽  
pp. 2151-2155 ◽  
Author(s):  
S. Dutta ◽  
K. S. Narayan
2006 ◽  
Vol 88 (24) ◽  
pp. 243507 ◽  
Author(s):  
K. S. Narayan ◽  
Manohar Rao ◽  
R. Zhang ◽  
P. Maniar

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1520011 ◽  
Author(s):  
Pial Mirdha ◽  
Murali Lingalugari ◽  
Evan K. Heller ◽  
John A. Chandy ◽  
Faquir C. Jain

In this paper, we propose a multiplexer design based on use of a twin channel and twin drain spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFET comprises of vertically stacked coupled quantum wells devices, which are the channels, where depending on the gate voltage only one of the channels is in conduction mode. Using SWSFET in multi-channel and single drain configuration operates as a multi-valued logic device. 2:1 and 4:2 multiplexer designs are proposed which are compatible with current CMOS technology and with all SWSFET. Both designs lead to greater than 4X reduction in transistor count. Ngspice simulation of circuits is also presented.


2007 ◽  
Vol 244 (11) ◽  
pp. 4188-4192 ◽  
Author(s):  
M. Y. Zavodchikova ◽  
A. Johansson ◽  
M. Rinkiö ◽  
J. J. Toppari ◽  
A. G. Nasibulin ◽  
...  

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