scholarly journals Size-Scalable and High-Density Liquid-Metal-Based Soft Electronic Passive Components and Circuits Using Soft Lithography

2016 ◽  
Vol 27 (3) ◽  
pp. 1604466 ◽  
Author(s):  
Min-gu Kim ◽  
Hommood Alrowais ◽  
Spyridon Pavlidis ◽  
Oliver Brand
Keyword(s):  
Liquid Metal ◽  
Soft Lithography ◽  
High Density ◽  
Passive Components

Design Considerations and Ring-down Characteristics of Micromachined, High Current Density Capacitors

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001380-001406
Author(s):  
Aubrey N. Beal ◽  
John Tatarchuk ◽  
Colin Stevens ◽  
Thomas Baginski ◽  
Michael Hamilton ◽  
...  
Keyword(s):  
Energy Storage ◽  
Surface Area ◽  
High Density ◽  
Energy Storage Devices ◽  
Capacitive Energy Storage ◽  
Passive Components ◽  
Storage Devices ◽  
Passive Devices ◽  
High K ◽  
High K Materials

The need for integrated passive components which meet the stringent power system requirements imposed by increased data rates, signal path density and challenging power distribution network topologies in integrated systems yield diverse motivations for high density, miniaturized capacitors capable of quickly sourcing large quantities of current. These diverse motivations have led to the realization of high density capacitor structures through the means of several technologies. These structures have been evaluated as high-speed, energy storage devices and their respective fabrication technologies have been closely compared for matching integrated circuit speed and density increase, chip current requirements, low resistance, low leakage current, high capacitance and compatibility with relatively high frequencies of operation (~1GHz). These technologies include devices that utilize pn junctions, Schottky barriers, optimized surface area techniques and the utilization of high dielectric constant (high-K) materials, such as hafnium oxide, as a dielectric layer through the means of atomic layer deposition (ALD). The resulting devices were micro-machined, large surface area, thin, high-density capacitor technologies optimized as embedded passive devices for thin silicon interposers. This work outlines the design, fabrication, simulation and testing of each device revision using standard silicon microfabrication processes and silicon interposer technologies. Consequently, capacitive storage devices were micro-machined with geometries which maximize surface area and exhibit the capability of sourcing 100A of current with a response time greater than 100 A/nsec through the use of thin layered, ALD high-K materials. The simulation and testing of these devices show general agreement when subjected to a standard ring-down procedure. This paper provides descriptions and design challenges encountered during fabrication, testing and integration of these passive devices. In addition, potential device integration and implementation strategies for use in silicon interposers are also provided. The modification and revision of several device generations is documented showing increased device capacitance density, maximized current capabilities and minimized effects of series inductance and resistance. The resulting structures are thin, capacitive devices that may be micro-machined using industry standard Si MEMS processes and are compatible with Si interposer 3D technologies. The subsequent design processes allow integrated passive components to be attached beneath chips in order to maximize system area and minimize the chip real estate required for capacitive energy storage devices.

scholarly journals High Density Packaging of the Passive Components in an Automotive DC/DC Converter

2005 ◽  
Vol 20 (2) ◽  
pp. 268-275 ◽  
Author(s):  
M. Gerber ◽  
J.A. Ferreira ◽  
I.W. Hofsajer ◽  
N. Seliger
Keyword(s):  
High Density ◽  
Passive Components ◽  
High Density Packaging

Thermal Management in High-Density, Stacked-Die, Multi-chip Modules

2006 ◽  
Vol 968 ◽  
Author(s):  
Thomas Marinis ◽  
Dariusz Pryputniewicz ◽  
Caroline Kondoleon ◽  
Jason Haley
Keyword(s):  
Thermal Management ◽  
Heat Removal ◽  
High Density ◽  
Base Layer ◽  
Copper Metallization ◽  
Thermal Impedance ◽  
Passive Components ◽  
Module Design ◽  
Higher Power ◽  
Module Performance

ABSTRACTVery high density multi-chip modules are being manufactured by tiling an alumina substrate with IC chips and passive components, laminating a film of Kapton over them, laser drilling vias to their I/O pads, and interconnecting them with photo patterned, copper metallization. Additional layers of components and interconnects are added on top of the base layer, as needed, to allow greater integration of large circuits. Current products are typically two layers of chips and seven layers of interconnect. As higher power applications have emerged and the power density of IC chips has increased, thermal management has become a significant factor impacting module design. We have been conducting a thermal modeling effort to map the design space for this technology. Our principal objective is to define and evaluate low thermal impedance (heat removal) configurations for a given chip set. A second objective is to determine what gains in module performance might be realized by improvements in material properties or changes in the relative thicknesses of dielectric and metal layers.

FERROELECTRIC THIN FILM SYSTEM IN PACKAGE DEVICES WITH INTEGRATED CAPACITORS OF 100 nF/mm2 & BREAKDOWN VOLTAGES OF 90 V

2007 ◽  
Vol 1034 ◽  
Author(s):  
Mareike Klee ◽  
Wilco Keur ◽  
Ruediger Mauczok ◽  
Aarnoud Roest ◽  
Klaus Reimann ◽  
...  
Keyword(s):  
Thin Film ◽  
Breakdown Voltage ◽  
Ferroelectric Thin Film ◽  
High Density ◽  
Film System ◽  
Passive Components ◽  
Thin Film System ◽  
Space Saving ◽  
The World ◽  
Ferroelectric Capacitors

AbstractThin film ferroelectric capacitors have been integrated with resistors and active functions such as ESD protection into small miniaturized modules, which enable a board space saving of up to 80%. With the optimum materials and processes, integrated capacitors with capacitance densities of up to 100 nF/mm2 and breakdown voltages of up to 90 V have been achieved. The integration of these high density capacitors with extremely high breakdown voltage is a revolution in the world of integrated passive components and has not yet been achieved in any other passive integration technology.

3D printed RF passive components by liquid metal filling

2015 ◽  
Author(s):  
Chen Yang ◽  
Sung-Yueh Wu ◽  
Casey Glick ◽  
Yun Seok Choi ◽  
Wensyang Hsu ◽  
...  
Keyword(s):  
Liquid Metal ◽  
Passive Components ◽  
3D Printed

Two-fluid model studies for high density two-phase liquid metal vertical flows

1998 ◽  
Vol 24 (5) ◽  
pp. 721-737 ◽  
Author(s):  
P. Satyamurthy ◽  
N.S. Dixit ◽  
T.K. Thiyagarajan ◽  
N. Venkatramani ◽  
A.M. Quraishi ◽  
...  
Keyword(s):  
Liquid Metal ◽  
Fluid Model ◽  
High Density ◽  
Two Phase ◽  
Model Studies ◽  
Phase Liquid ◽  
Two Fluid Model ◽  
Two Fluid

Wire Bonding Looping Solutions for High Density System-in-Package (SiP)

2017 ◽  
Vol 2017 (1) ◽  
pp. 000426-000431 ◽  
Author(s):  
Basil Milton ◽  
Odal Kwon ◽  
Cuong Huynh ◽  
Ivy Qin ◽  
Bob Chylak
Keyword(s):  
System Integration ◽  
3D Visualization ◽  
Wire Bonding ◽  
High Density ◽  
Wire Length ◽  
Loop Formation ◽  
Passive Components ◽  
Wire Bond ◽  
Design Software ◽  
The Wire

Abstract System-in-Package (SiP) have seen a lot of growth in recent years especially in mobile devices due to its higher level of system integration, more design flexibility and smaller form factor. Two or more semiconductor die and passive components are usually present in a SiP device. Die to die bonding and increased I/O density are two common challenges associated with wire bonding in SiPs. High density SiP packages often have high I/O counts and tight wire clearance. As a result, the requirements for wire bond looping are high. To avoid wire shorts, the wire bond loops need to be well designed in order to have optimal wire clearance between various tiers of wire loops as well as neighboring loops. The formed loops need to have low wire sway after wire bonding and low wire sweep after molding. Due to the existence of multiple dies and other passive components within the same package, special wire bond loops with long flat lengths and sharp bending angles are sometimes necessary to clear the die edges and the other components. In this paper, we will review a few new wire bonding looping solutions including 3D looping design software, 3D loop clearance checking and multi-tier loop formation improvements. A robust package design is essential to improve production yield. A 3D looping design software has been developed to evaluate the robustness of various package designs from a wire looping perspective. The software is able to detect potential issues early on in the design cycle and evaluate alternatives quickly, therefore reduces the time to market and improves design robustness. A spatial 3D clearance checking tool has been developed to detect any interference between the densely populated wire loops. The tool can also detect interference between the wires and the edges of different dies. Furthermore, the wire clearance against various components in the package can also be assessed. Process engineers can leverage the clearance check tool and the 3D visualization of wires, multiple dies and components to aid wire bonding looping optimization. Multi-tier looping requires a large range of loop height and wire length capability. In order to achieve optimal looping for high density multi-tier applications, a separate wire bonding looping software has been developed to generate optimal wire bonding motion trajectories that can achieve the loop shapes designed by the 3D looping design software. An example of 6 loop tier application is developed and results are analyzed to show the wire bonding capabilities including looping height from 75um to 500um and wire length up to 5mm.

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