Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By ACM Press

9781450339636

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

System-Level Analysis of Network Interfaces for Hierarchical MPSoCs

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15 ◽

10.1145/2835512.2835513 ◽

2015 ◽

Cited By ~ 4

Author(s):

Johannes Ax ◽

Gregor Sievers ◽

Martin Flasskamp ◽

Wayne Kelly ◽

Thorsten Jungeblut ◽

...

Keyword(s):

System Level ◽

Network Interfaces ◽

Level Analysis

Download Full-text

Automated Power and Latency Management in Heterogeneous 3D NoCs

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15 ◽

10.1145/2835512.2835517 ◽

2015 ◽

Author(s):

Awet Yemane WeldeZion ◽

Masoumeh Ebrahimi ◽

Masoud Daneshtalab ◽

Hannu Tenhunen

Download Full-text

Task mapping and communication routing model for minimizing power consumption in multi-cores

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15 ◽

10.1145/2835512.2835515 ◽

2015 ◽

Cited By ~ 1

Author(s):

Sergiu Carpov

Keyword(s):

Power Consumption ◽

Task Mapping

Download Full-text

NoCVision

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15 ◽

10.1145/2835512.2835518 ◽

2015 ◽

Author(s):

Vaibhav Gogte ◽

Doowon Lee ◽

Ritesh Parikh ◽

Valeria Bertacco

Download Full-text

A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15 ◽

10.1145/2835512.2835519 ◽

2015 ◽

Author(s):

Jian Jie ◽

Lai Mingche ◽

Xiao Liquan

Keyword(s):

Quality Of Service ◽

High Throughput ◽

Low Latency ◽

Multiple Level ◽

On Chip

Download Full-text

Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15 ◽

10.1145/2835512.2835514 ◽

2015 ◽

Author(s):

Poona Bahrebar ◽

Dirk Stroobandt

Keyword(s):

Cost Effective ◽

Networks On Chip ◽

On Chip ◽

3D Networks

Download Full-text

Methodology to verify, debug and evaluate performances of NoC based interconnects

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15 ◽

10.1145/2835512.2835521 ◽

2015 ◽

Author(s):

Patrick Oury ◽

Nick Heaton ◽

Stewart Penman

Download Full-text

Rethinking Memory System Design (along with Interconnects)

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15 ◽

10.1145/2835512.2835520 ◽

2015 ◽

Author(s):

Onur Mutlu

Keyword(s):

System Design ◽

Memory System ◽

Memory System Design

Download Full-text

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

System-Level Analysis of Network Interfaces for Hierarchical MPSoCs

Automated Power and Latency Management in Heterogeneous 3D NoCs

Task mapping and communication routing model for minimizing power consumption in multi-cores

NoCVision

A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network

Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip

Methodology to verify, debug and evaluate performances of NoC based interconnects

Rethinking Memory System Design (along with Interconnects)

Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15
Latest Publications