Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.
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Published By IEEE Comput. Soc

0780376552

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An effective and flexible approach to functional verification of processor families

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224435 ◽

2003 ◽

Cited By ~ 4

Author(s):

D. Malandain ◽

P. Palmen ◽

M. Taylor ◽

M. Aharoni ◽

Y. Arbetman ◽

...

Keyword(s):

Functional Verification ◽

Flexible Approach

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A 1000X speed up for properties completeness evaluation

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224422 ◽

2003 ◽

Cited By ~ 4

Author(s):

A. Castelnuovo ◽

A. Fedeli ◽

A. Fin ◽

F. Fummi ◽

G. Pravadelli ◽

...

Keyword(s):

Speed Up

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Verification of a DSP IP cores by model checking

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224440 ◽

2003 ◽

Author(s):

H.N. Nguyen ◽

P. Koumou ◽

B. Candaele ◽

M. Sarlotte ◽

C. Antoine ◽

...

Keyword(s):

Model Checking ◽

Ip Cores

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Test generation for hardware-software covalidation using non-linear programming

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224449 ◽

2003 ◽

Cited By ~ 2

Author(s):

Fei Xin ◽

I.G. Harris

Keyword(s):

Linear Programming ◽

Test Generation ◽

Non Linear Programming ◽

Non Linear

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Alignability equivalence of synchronous sequential circuits

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224438 ◽

2003 ◽

Cited By ~ 6

Author(s):

A. Rosenmann ◽

Z. Hanna

Keyword(s):

Sequential Circuits ◽

Synchronous Sequential Circuits

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Adaptive test program generation: planning for the unplanned

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224433 ◽

2003 ◽

Cited By ~ 2

Author(s):

A. Adir ◽

R. Emek ◽

E. Marcus

Keyword(s):

Test Program ◽

Program Generation ◽

Adaptive Test ◽

Generation Planning

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Constructing reusable testbenches

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224445 ◽

2003 ◽

Author(s):

A. Wakefield ◽

B.J. Mohd

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Timed HW-SW cosimulation using native execution of OS and application SW

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224428 ◽

2003 ◽

Cited By ~ 9

Author(s):

M. Bacivarov ◽

Sungjoo Yoo ◽

A.A. Jerraya

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Formal analysis and validation of continuous-time Markov chain based system level power management strategies

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224427 ◽

2003 ◽

Cited By ~ 13

Author(s):

G. Norman ◽

D. Parker ◽

M. Kwiatkowska ◽

S.K. Shukla ◽

R.K. Gupta

Keyword(s):

Markov Chain ◽

Power Management ◽

Continuous Time ◽

Formal Analysis ◽

Management Strategies ◽

System Level ◽

Continuous Time Markov Chain

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TRANS: efficient sequential verification of loop-free circuits

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. ◽

10.1109/hldvt.2002.1224439 ◽

2003 ◽

Cited By ~ 2

Author(s):

Z. Khasidashvili ◽

J. Moondanos ◽

Z. Hanna

Download Full-text

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

An effective and flexible approach to functional verification of processor families

A 1000X speed up for properties completeness evaluation

Verification of a DSP IP cores by model checking

Test generation for hardware-software covalidation using non-linear programming

Alignability equivalence of synchronous sequential circuits

Adaptive test program generation: planning for the unplanned

Constructing reusable testbenches

Timed HW-SW cosimulation using native execution of OS and application SW

Formal analysis and validation of continuous-time Markov chain based system level power management strategies

TRANS: efficient sequential verification of loop-free circuits

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.
Latest Publications