Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14
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Published By ACM Press

9781450330534

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Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14 ◽

10.1145/2633948.2633950 ◽

2014 ◽

Cited By ~ 2

Author(s):

Xiang Zhang ◽

Jingwei Lu ◽

Yang Liu ◽

Chung-Kuan Cheng

Keyword(s):

Power Distribution ◽

Distribution Network ◽

Power Distribution Network ◽

Worst Case ◽

On Chip

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Compact Models and Model Standard for 2.5D and 3D Integration

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14 ◽

10.1145/2633948.2633955 ◽

2014 ◽

Author(s):

Qiaosha Zou ◽

Yuan Xie

Keyword(s):

3D Integration ◽

Compact Models

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PACMAN

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14 ◽

10.1145/2633948.2633951 ◽

2014 ◽

Cited By ~ 2

Author(s):

Nancy Y. Zhou ◽

Phillip Restle ◽

Joseph Palumbo ◽

Joseph Kozhaya ◽

Haifeng Qian ◽

...

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Range-based Dynamic Routing of Hierarchical On Chip Network Traffic

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14 ◽

10.1145/2633948.2633953 ◽

2014 ◽

Cited By ~ 1

Author(s):

Julian Kemmerer ◽

Baris Taskin

Keyword(s):

Network Traffic ◽

Dynamic Routing ◽

On Chip

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UI-Route

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14 ◽

10.1145/2633948.2633952 ◽

2014 ◽

Cited By ~ 1

Author(s):

Tsung-Wei Huang ◽

Pei-Ci Wu ◽

Martin D. F. Wong

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Power Network-on-Chip for Scalable Power Delivery

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14 ◽

10.1145/2633948.2633949 ◽

2014 ◽

Cited By ~ 2

Author(s):

Inna Vaisband ◽

Eby G. Friedman

Keyword(s):

Network On Chip ◽

Power Delivery ◽

Power Network ◽

On Chip

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Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14 ◽

10.1145/2633948.2633954 ◽

2014 ◽

Cited By ~ 3

Author(s):

Wei-Ting Jonas Chan ◽

Andrew B. Kahng ◽

Siddhartha Nath

Keyword(s):

Voltage Scaling

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Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Compact Models and Model Standard for 2.5D and 3D Integration

PACMAN

Range-based Dynamic Routing of Hierarchical On Chip Network Traffic

UI-Route

Power Network-on-Chip for Scalable Power Delivery

Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14
Latest Publications