Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10
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Published By ACM Press

9781450300087

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Comparing last-level cache designs for CMP architectures

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10 ◽

10.1145/1882453.1882456 ◽

2010 ◽

Cited By ~ 2

Author(s):

Augusto Vega ◽

Alejandro Rico ◽

Felipe Cabarcas ◽

Alex Ramírez ◽

Mateo Valero

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LV*

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10 ◽

10.1145/1882453.1882460 ◽

2010 ◽

Cited By ~ 1

Author(s):

Anurag Negi ◽

M. M. Waliullah ◽

Per Stenstrom

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SCMP architecture

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10 ◽

10.1145/1882453.1882461 ◽

2010 ◽

Cited By ~ 5

Author(s):

Nicolas Ventroux ◽

Raphaël David

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Fitting FFT onto an energy efficient massively parallel architecture

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10 ◽

10.1145/1882453.1882464 ◽

2010 ◽

Cited By ~ 1

Author(s):

István Lőrentz ◽

Mihaela Maliţa ◽

Rǎzvan Andonie

Keyword(s):

Energy Efficient ◽

Parallel Architecture ◽

Massively Parallel

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An adaptive cache coherence protocol for chip multiprocessors

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10 ◽

10.1145/1882453.1882458 ◽

2010 ◽

Cited By ~ 3

Author(s):

Abdullah Kayi ◽

Tarek El-Ghazawi

Keyword(s):

Chip Multiprocessors ◽

Cache Coherence ◽

Cache Coherence Protocol ◽

Adaptive Cache

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Power and performance aware reconfigurable cache for CMPs

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10 ◽

10.1145/1882453.1882455 ◽

2010 ◽

Cited By ~ 6

Author(s):

Kamil Kędzierski ◽

Francisco J. Cazorla ◽

Roberto Gioiosa ◽

Alper Buyuktosunoglu ◽

Mateo Valero

Keyword(s):

And Performance ◽

Reconfigurable Cache

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Accelerating data movement on future chip multi-processors

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10 ◽

10.1145/1882453.1882457 ◽

2010 ◽

Author(s):

Junli Gu ◽

Rakesh Kumar ◽

Steven S. Lumetta ◽

Yihe Sun

Keyword(s):

Data Movement

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Efficient parallel selective separable-kernel convolution on heterogeneous processors

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10 ◽

10.1145/1882453.1882463 ◽

2010 ◽

Author(s):

Ahmed El-Mahdy ◽

Hisham El-Shishiny

Keyword(s):

Heterogeneous Processors ◽

Kernel Convolution ◽

Separable Kernel

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Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Comparing last-level cache designs for CMP architectures

LV*

SCMP architecture

Fitting FFT onto an energy efficient massively parallel architecture

An adaptive cache coherence protocol for chip multiprocessors

Power and performance aware reconfigurable cache for CMPs

Accelerating data movement on future chip multi-processors

Efficient parallel selective separable-kernel convolution on heterogeneous processors

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies - IFMT '10
Latest Publications