Proceedings Seventeenth Conference on Advanced Research in VLSI
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A high-speed asynchronous decompression circuit for embedded processors

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634856 ◽

2002 ◽

Cited By ~ 9

Author(s):

M. Benes ◽

A. Wolfe ◽

S.M. Nowick

Keyword(s):

High Speed ◽

Embedded Processors

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Asynchronous microengines for efficient high-level control

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634855 ◽

2002 ◽

Cited By ~ 2

Author(s):

I. Jacobson ◽

G. Gopalakrishnan

Keyword(s):

Level Control ◽

High Level

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Pipelined multi-queue management in a VLSI ATM switch chip with credit-based flow-control

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634851 ◽

2002 ◽

Cited By ~ 11

Author(s):

G. Kornaros ◽

C. Kozyrakis ◽

P. Vatsolaki ◽

M. Katevenis

Keyword(s):

Flow Control ◽

Queue Management ◽

Atm Switch

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Clock distribution using cooperative ring oscillators

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634846 ◽

2002 ◽

Cited By ~ 16

Author(s):

L. Hall ◽

M. Clements ◽

Wentai Liu ◽

G. Bilbro

Keyword(s):

Ring Oscillators ◽

Clock Distribution

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Design implementation of intrinsic area array ICs

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634848 ◽

2002 ◽

Cited By ~ 11

Author(s):

C. Tan ◽

D. Bouldin ◽

P. Dehkordi

Keyword(s):

Area Array

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The design of an asynchronous MIPS R3000 microprocessor

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634853 ◽

2002 ◽

Cited By ~ 208

Author(s):

A.J. Martin ◽

A. Lines ◽

R. Manohar ◽

M. Nystrom ◽

P. Penzes ◽

...

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A VLSI architecture for modeling intersegmental coordination

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634854 ◽

2002 ◽

Cited By ~ 6

Author(s):

S.P. DeWeerth ◽

G.N. Patel ◽

M.F. Simoni ◽

D.E. Schimmel ◽

R.L. Calabrese

Keyword(s):

Vlsi Architecture ◽

Intersegmental Coordination

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Scalability in computing for today and tomorrow

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634843 ◽

2002 ◽

Cited By ~ 1

Author(s):

D. Parry

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The hierarchical multi-bank DRAM: a high-performance architecture for memory integrated with processors

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634862 ◽

2002 ◽

Cited By ~ 15

Author(s):

T. Yamauchi ◽

L. Hammond ◽

K. Olukotun

Keyword(s):

High Performance

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Circuits and microarchitecture for gigahertz VLSI designs

Proceedings Seventeenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1997.634860 ◽

2002 ◽

Author(s):

K.J. Nowka ◽

H.P. Hofstee

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Proceedings Seventeenth Conference on Advanced Research in VLSILatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A high-speed asynchronous decompression circuit for embedded processors

Asynchronous microengines for efficient high-level control

Pipelined multi-queue management in a VLSI ATM switch chip with credit-based flow-control

Clock distribution using cooperative ring oscillators

Design implementation of intrinsic area array ICs

The design of an asynchronous MIPS R3000 microprocessor

A VLSI architecture for modeling intersegmental coordination

Scalability in computing for today and tomorrow

The hierarchical multi-bank DRAM: a high-performance architecture for memory integrated with processors

Circuits and microarchitecture for gigahertz VLSI designs

Proceedings Seventeenth Conference on Advanced Research in VLSI
Latest Publications