1991 Proceedings, International Conference on Wafer Scale Integration
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Published By IEEE Comput. Soc. Press

0818691263

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Silicon substrate test structures for hybrid wafer scale technology

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151714 ◽

2002 ◽

Cited By ~ 6

Author(s):

M.J. Davies ◽

A.G. Munns ◽

D.J. Pedder

Keyword(s):

Silicon Substrate ◽

Wafer Scale

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VHDL-based design and analysis of defect tolerant VLSI/WSI array architectures

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151711 ◽

2002 ◽

Author(s):

S.-Y. Kuo ◽

K. Wang

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Reconfiguration of binary trees: the flow-driven approach

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151708 ◽

2002 ◽

Author(s):

A. Antola ◽

N. Scarabottolo

Keyword(s):

Binary Trees

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A rapid prototype wafer scale system design for signal and data processing

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151698 ◽

2002 ◽

Author(s):

D. Landis ◽

H. Brown ◽

T. Sanders ◽

M. Shahsavari ◽

J. Hadjilogiou ◽

...

Keyword(s):

Data Processing ◽

System Design ◽

Rapid Prototype ◽

Wafer Scale

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Efficient reconfiguration algorithms for degradable VLSI/WSI arrays

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151705 ◽

2002 ◽

Cited By ~ 6

Author(s):

S.-Y. Kuo ◽

I.-Y. Chen

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Rotary spare replacement redundancy for tree architecture WSIs

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151700 ◽

2002 ◽

Cited By ~ 3

Author(s):

N. Tsuda

Keyword(s):

Tree Architecture

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Wafer scale integration-a technology whose time has come

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151735 ◽

2002 ◽

Cited By ~ 1

Author(s):

P.J. Cavill ◽

P.E. Stapleton ◽

J.M. Wilkinson

Keyword(s):

Wafer Scale ◽

Wafer Scale Integration ◽

Scale Integration

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Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151704 ◽

2002 ◽

Cited By ~ 5

Author(s):

F. Distante ◽

M.G. Sami ◽

R. Stefanelli ◽

G. Storti Gajani

Keyword(s):

Linear Array ◽

Fault Tolerant ◽

Neural Nets ◽

Array Architecture

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WSI systolic networks: an active silicon circuit board function for ULSI-based parallel computing

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151726 ◽

2002 ◽

Author(s):

S.K. Tewksbury

Keyword(s):

Parallel Computing ◽

Circuit Board

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Universal switching network: application to a WSI SIMD array

1991 Proceedings, International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1991.151724 ◽

2002 ◽

Cited By ~ 4

Author(s):

A. Boubekeur ◽

J.-L. Patry ◽

G. Saucier ◽

J. Trilhe

Keyword(s):

Switching Network ◽

Network Application

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1991 Proceedings, International Conference on Wafer Scale IntegrationLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Silicon substrate test structures for hybrid wafer scale technology

VHDL-based design and analysis of defect tolerant VLSI/WSI array architectures

Reconfiguration of binary trees: the flow-driven approach

A rapid prototype wafer scale system design for signal and data processing

Efficient reconfiguration algorithms for degradable VLSI/WSI arrays

Rotary spare replacement redundancy for tree architecture WSIs

Wafer scale integration-a technology whose time has come

Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets

WSI systolic networks: an active silicon circuit board function for ULSI-based parallel computing

Universal switching network: application to a WSI SIMD array

1991 Proceedings, International Conference on Wafer Scale Integration
Latest Publications