Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00
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Prove that a faulty multiplier is faulty!?

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.330957 ◽

2000 ◽

Cited By ~ 3

Author(s):

Sandro Wefel ◽

Paul Molitor

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Impact of internet on EDA research and development (keynote address) (abstract only)

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.332571 ◽

2000 ◽

Author(s):

Naveed Sherwani

Keyword(s):

Research And Development ◽

Keynote Address

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Digital CMOS logic operation in the sub-threshold region

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.331014 ◽

2000 ◽

Cited By ~ 25

Author(s):

Hendrawan Soeleman ◽

Kaushik Roy

Keyword(s):

Threshold Region ◽

Digital Cmos ◽

Logic Operation

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Low power and high performance design challenges in future technologies

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.330929 ◽

2000 ◽

Cited By ~ 18

Author(s):

Vivek De ◽

Shekhar Borkar

Keyword(s):

Low Power ◽

High Performance ◽

Future Technologies ◽

Design Challenges ◽

High Performance Design

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Accuracy management for mixed-mode digital VLSI simulation

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.331033 ◽

2000 ◽

Author(s):

Gary L. Dare ◽

Charles A. Zukowski

Keyword(s):

Mixed Mode ◽

Digital Vlsi

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CMOS system-on-a-chip voltage scaling beyond 50nm

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.332574 ◽

2000 ◽

Cited By ~ 2

Author(s):

Azeez J. Bhavnagarwala ◽

Blanca Austin ◽

Ashok Kapoor ◽

James D. Meindl

Keyword(s):

Voltage Scaling ◽

System On A Chip

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Behavioral-level partitioning for low power design in control-dominated application

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.331028 ◽

2000 ◽

Cited By ~ 1

Author(s):

Ki-Seok Chung ◽

Taewhan Kim ◽

C. I. Liu

Keyword(s):

Low Power ◽

Low Power Design ◽

Behavioral Level

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Towards design and validation of mixed-technology SOCs

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.330950 ◽

2000 ◽

Cited By ~ 6

Author(s):

S. Mir ◽

B. Charlot ◽

G. Nicolescu ◽

P. Coste ◽

F. Parrain ◽

...

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Technology independent arbitrary device extractor

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.331023 ◽

2000 ◽

Cited By ~ 4

Author(s):

Qiao Li ◽

Sung-Mo Kang

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On-chip inductance modeling

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.330980 ◽

2000 ◽

Cited By ~ 1

Author(s):

David Blaauw ◽

Kaushik Gala ◽

Vladimir Zolotov ◽

Rajendran Panda ◽

Junfeng Wang

Keyword(s):

On Chip

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Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Prove that a faulty multiplier is faulty!?

Impact of internet on EDA research and development (keynote address) (abstract only)

Digital CMOS logic operation in the sub-threshold region

Low power and high performance design challenges in future technologies

Accuracy management for mixed-mode digital VLSI simulation

CMOS system-on-a-chip voltage scaling beyond 50nm

Behavioral-level partitioning for low power design in control-dominated application

Towards design and validation of mixed-technology SOCs

Technology independent arbitrary device extractor

On-chip inductance modeling

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00
Latest Publications