Interaction between Compilers and Computer Architectures
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Published By Springer US

9781441948960, 9781475733372

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Is Compiling for Performance — Compiling for Power?

Interaction between Compilers and Computer Architectures ◽

10.1007/978-1-4757-3337-2_6 ◽

2001 ◽

pp. 101-115 ◽

Cited By ~ 36

Author(s):

Madhavi Valluri ◽

Lizy K. John

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Equimax: A New Formulation of Optimal Register-Sensitive Scheduling for ILP Processors

Interaction between Compilers and Computer Architectures ◽

10.1007/978-1-4757-3337-2_1 ◽

2001 ◽

pp. 1-19 ◽

Cited By ~ 1

Author(s):

Sid-Ahmed-Ali Touati

Keyword(s):

New Formulation

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Register Allocation for Embedded System in the Presence of Java Exception

Interaction between Compilers and Computer Architectures ◽

10.1007/978-1-4757-3337-2_5 ◽

2001 ◽

pp. 89-100

Author(s):

Heung-Bok Lee ◽

Byung-Sun Yang ◽

Soo-Mook Moon

Keyword(s):

Embedded System ◽

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Impact of Tile-Size Selection for Skewed Tiling

Interaction between Compilers and Computer Architectures ◽

10.1007/978-1-4757-3337-2_3 ◽

2001 ◽

pp. 45-68 ◽

Cited By ~ 4

Author(s):

Yonghong Song ◽

Zhiyuan Li

Keyword(s):

Size Selection ◽

Tile Size ◽

Selection For

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An Efficient Semi-Hierarchical Array Layout

Interaction between Compilers and Computer Architectures ◽

10.1007/978-1-4757-3337-2_2 ◽

2001 ◽

pp. 21-43

Author(s):

N. P. Drakenberg ◽

F. Lundevall ◽

B. Lisper

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A Technology-Scalable Architecture for Fast Clocks and High ILP

Interaction between Compilers and Computer Architectures ◽

10.1007/978-1-4757-3337-2_7 ◽

2001 ◽

pp. 117-139 ◽

Cited By ~ 5

Author(s):

Karthikeyan Sankaralingam ◽

Ramadass Nagarajan ◽

Doug Burger ◽

Stephen W. Keckler

Keyword(s):

Scalable Architecture

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Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches

Interaction between Compilers and Computer Architectures ◽

10.1007/978-1-4757-3337-2_4 ◽

2001 ◽

pp. 69-87 ◽

Cited By ~ 1

Author(s):

Michael Bedy ◽

Steve Carr ◽

Soner Önder ◽

Philip Sweany

Keyword(s):

Software Pipelining ◽

Memory Latency ◽

Combined Loads

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Interaction between Compilers and Computer ArchitecturesLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer US

Is Compiling for Performance — Compiling for Power?

Equimax: A New Formulation of Optimal Register-Sensitive Scheduling for ILP Processors

Register Allocation for Embedded System in the Presence of Java Exception

Impact of Tile-Size Selection for Skewed Tiling

An Efficient Semi-Hierarchical Array Layout

A Technology-Scalable Architecture for Fast Clocks and High ILP

Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches

Interaction between Compilers and Computer Architectures
Latest Publications