[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture
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Published By IEEE Comput. Soc. Press

0818621249

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A weighted technique for programmable logic devices minimization

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151453 ◽

2002 ◽

Cited By ~ 1

Author(s):

C.H. Chang ◽

H.K. Azzam

Keyword(s):

Programmable Logic ◽

Logic Devices ◽

Programmable Logic Devices

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An evaluation of functional unit lengths for single-chip processors

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151444 ◽

2002 ◽

Author(s):

M.K. Farrens ◽

A.R. Pleszkun

Keyword(s):

Functional Unit ◽

Single Chip

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A multiple floating point coprocessor architecture

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151445 ◽

2002 ◽

Author(s):

L. Rauchwerger ◽

P.M. Farmwald

Keyword(s):

Floating Point

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An application of L systems to local microcode synthesis

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151439 ◽

2002 ◽

Cited By ~ 1

Author(s):

F. Mavaddat ◽

M. Mahmood ◽

M.H.M. Cheng

Keyword(s):

L Systems

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Using a lookahead window in a compaction-based parallelizing compiler

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151427 ◽

2002 ◽

Cited By ~ 14

Author(s):

T. Nakatani ◽

K. Ebcioglu

Keyword(s):

Parallelizing Compiler

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A memory management unit and cache controller for the MARS system

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151443 ◽

2002 ◽

Author(s):

Feipei Lai ◽

Chyuan-Yow Wu ◽

Tai-Ming Parng

Keyword(s):

Memory Management ◽

Management Unit

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Interconnection synthesis with geometric constraints

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151438 ◽

2002 ◽

Cited By ~ 1

Author(s):

F. Brewer ◽

B. Pangrle ◽

A. Seawright

Keyword(s):

Geometric Constraints

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A software pipelining based VLIW architecture and optimizing compiler

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151423 ◽

2002 ◽

Cited By ~ 1

Author(s):

Bogong Su ◽

Jian Wang ◽

Zhizhong Tang ◽

Wei Zhao ◽

Yimin Wu

Keyword(s):

Software Pipelining ◽

Optimizing Compiler

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Optimization on instruction reorganization

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151436 ◽

2002 ◽

Author(s):

F. Lai ◽

Hung-Chang Lee ◽

Chun-Luh Lee

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VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture ◽

10.1109/micro.1990.151422 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Danelutto ◽

M. Vanneschi

Keyword(s):

Distributed Memory ◽

Fine Grain

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[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and MicroarchitectureLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

A weighted technique for programmable logic devices minimization

An evaluation of functional unit lengths for single-chip processors

A multiple floating point coprocessor architecture

An application of L systems to local microcode synthesis

Using a lookahead window in a compaction-based parallelizing compiler

A memory management unit and cache controller for the MARS system

Interconnection synthesis with geometric constraints

A software pipelining based VLIW architecture and optimizing compiler

Optimization on instruction reorganization

VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture
Latest Publications