2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design

2T-FN eNVM with 90 nm Logic Process for Smart Card

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.13 ◽

2008 ◽

Cited By ~ 6

Author(s):

Yong Kyu Lee ◽

Jung Ho Moon ◽

Young Ho Kim ◽

Myung-Jo Chun ◽

Soung-Youb Ha ◽

...

Keyword(s):

Smart Card ◽

Logic Process

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Advantage of Floating Gate B4-Flash over Retention Reliability after Cycling - Characterization by Variation of Transconductance

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.10 ◽

2008 ◽

Cited By ~ 5

Author(s):

S. Shukuri ◽

N. Ajika ◽

S. Shimizu ◽

M. Mihara ◽

Y. Kawajiri ◽

...

Keyword(s):

Floating Gate

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3-D Channel Structure Flash Having Short Channel Effect Immunity and Low Random Telegraph Signal Noise

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.11 ◽

2008 ◽

Cited By ~ 3

Author(s):

Wookhyun Kwon ◽

Yun Heub Song ◽

Yimao Cai ◽

Wonhyung Ryu ◽

Younggoan Jang ◽

...

Keyword(s):

Channel Structure ◽

Short Channel ◽

Short Channel Effect ◽

Random Telegraph Signal ◽

Signal Noise ◽

Channel Effect

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Opportunities and Challenges in Multi-Times-Programmable Floating-Gate Logic Non-Volatile Memories

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.12 ◽

2008 ◽

Cited By ~ 7

Author(s):

Bin Wang ◽

Yanjun Ma

Keyword(s):

Floating Gate

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A 90nm Embedded Page Flash for EEPROM Replacement in System On Chip

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.14 ◽

2008 ◽

Cited By ~ 4

Author(s):

A. Conte ◽

G. Matranga ◽

D. De Costantini ◽

M. Micciche ◽

C. Ucciardello ◽

...

Keyword(s):

System On Chip ◽

On Chip

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In-Ga-O Based Double-Heater Phase Change Memory Cell

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.15 ◽

2008 ◽

Author(s):

S.-L. Wang ◽

C.-Y. Chen ◽

M.-K. Hsieh ◽

W.-C. Lee ◽

A. H. Kung ◽

...

Keyword(s):

Phase Change ◽

Phase Change Memory ◽

Memory Cell ◽

Change Memory

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Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.23 ◽

2008 ◽

Cited By ~ 1

Author(s):

Sung-Taeg Kang ◽

Jane Yater ◽

Cheongmin Hong ◽

James Shen ◽

Nicole Ellis ◽

...

Keyword(s):

High Performance ◽

Si Nanocrystal

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A Study of Sub-40nm FinFET BE-SONOS NAND Flash

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.39 ◽

2008 ◽

Cited By ~ 1

Author(s):

Tzu-Hsuan Hsu ◽

Hang-Ting Lue ◽

Wu-Chin Peng ◽

Cheng-Hung Tsai ◽

Ya-Chin King ◽

...

Keyword(s):

Nand Flash

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Evidence of the Prominent Role of the Time-Under-Melt Parameter in the Reset Switching of Phase-Change Line Cells

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.16 ◽

2008 ◽

Cited By ~ 1

Author(s):

L. Goux ◽

T. Gille ◽

D. Tio Castro ◽

G. A. M. Hurkx ◽

J. G. Lisoni ◽

...

Keyword(s):

Phase Change

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Study of Charge Trapping Vertical Location and Capture Efficiency of SONOS-Type Devices by Gate-Sensing and Channel-Sensing (GSCS) Method

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design ◽

10.1109/nvsmw.2008.41 ◽

2008 ◽

Cited By ~ 1

Author(s):

Hang-Ting Lue ◽

Pei-Ying Du ◽

Szu-Yu Wang ◽

Kuang-Yeu Hsieh ◽

Rich Liu ◽

...

Keyword(s):

Charge Trapping ◽

Capture Efficiency ◽

Channel Sensing ◽

Vertical Location

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2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

2T-FN eNVM with 90 nm Logic Process for Smart Card

Advantage of Floating Gate B4-Flash over Retention Reliability after Cycling - Characterization by Variation of Transconductance

3-D Channel Structure Flash Having Short Channel Effect Immunity and Low Random Telegraph Signal Noise

Opportunities and Challenges in Multi-Times-Programmable Floating-Gate Logic Non-Volatile Memories

A 90nm Embedded Page Flash for EEPROM Replacement in System On Chip

In-Ga-O Based Double-Heater Phase Change Memory Cell

Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

A Study of Sub-40nm FinFET BE-SONOS NAND Flash

Evidence of the Prominent Role of the Time-Under-Melt Parameter in the Reset Switching of Phase-Change Line Cells

Study of Charge Trapping Vertical Location and Capture Efficiency of SONOS-Type Devices by Gate-Sensing and Channel-Sensing (GSCS) Method

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2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

2T-FN eNVM with 90 nm Logic Process for Smart Card

Advantage of Floating Gate B4-Flash over Retention Reliability after Cycling - Characterization by Variation of Transconductance

3-D Channel Structure Flash Having Short Channel Effect Immunity and Low Random Telegraph Signal Noise

Opportunities and Challenges in Multi-Times-Programmable Floating-Gate Logic Non-Volatile Memories

A 90nm Embedded Page Flash for EEPROM Replacement in System On Chip

In-Ga-O Based Double-Heater Phase Change Memory Cell

Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

A Study of Sub-40nm FinFET BE-SONOS NAND Flash

Evidence of the Prominent Role of the Time-Under-Melt Parameter in the Reset Switching of Phase-Change Line Cells

Study of Charge Trapping Vertical Location and Capture Efficiency of SONOS-Type Devices by Gate-Sensing and Channel-Sensing (GSCS) Method

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design
Latest Publications