IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip

Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_1 ◽

2007 ◽

pp. 1-23 ◽

Cited By ~ 2

Author(s):

Sam Kavusi ◽

Kunal Ghosh ◽

Abbas Gamal

Keyword(s):

High Speed ◽

Dynamic Range ◽

High Dynamic Range ◽

Image Sensor ◽

Readout Circuits ◽

High Dynamic

Download Full-text

Logic Synthesis of EXOR Projected Sum of Products

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_14 ◽

2007 ◽

pp. 241-257

Author(s):

Anna Bernasconi ◽

Valentina Ciriani ◽

Roberto Cordone

Keyword(s):

Logic Synthesis ◽

Sum Of Products

Download Full-text

Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_7 ◽

2007 ◽

pp. 101-118 ◽

Cited By ~ 8

Author(s):

Lakshmi N. B. Chakrapani ◽

Jason George ◽

Bo Marr ◽

Bilge E. S. Akgul ◽

Krishna V. Palem

Keyword(s):

Cmos Technology ◽

Probabilistic Design ◽

Ic Design ◽

Future Directions

Download Full-text

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_20 ◽

2007 ◽

pp. 357-376 ◽

Cited By ~ 3

Author(s):

Ittetsu Taniguchi ◽

Keishi Sakanushi ◽

Kyoko Ueda ◽

Yoshinori Takeuchi ◽

Masaharu Imai

Keyword(s):

Reconfigurable Architecture ◽

Reconfigurable Processor ◽

Architecture Exploration

Download Full-text

Probabilistic amp; Statistical Design—the Wave of the Future

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_5 ◽

2007 ◽

pp. 69-79

Author(s):

Shekhar Borkar

Keyword(s):

Statistical Design ◽

The Future

Download Full-text

Oversampled Time Estimation Techniques for Precision Photonic Detectors

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_2 ◽

2007 ◽

pp. 25-35

Author(s):

Robert Henderson ◽

Bruce Rae ◽

David Renshaw ◽

Edoardo Charbon

Keyword(s):

Time Estimation ◽

Estimation Techniques

Download Full-text

Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_13 ◽

2007 ◽

pp. 217-240

Author(s):

Zeynep Toprak Deniz ◽

Yusuf Leblebici ◽

Eric Vittoz

Keyword(s):

Embedded Systems ◽

Energy Optimization ◽

Analog Computation ◽

Global Energy ◽

On Line

Download Full-text

Library Compatible Variational Delay Computation

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_10 ◽

2007 ◽

pp. 157-176 ◽

Cited By ~ 1

Author(s):

Luis Guerra e Silva ◽

Zhenhai Zhu ◽

Joel R. Phillips ◽

L. Miguel Silveira

Download Full-text

A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_11 ◽

2007 ◽

pp. 177-196

Author(s):

Giovanni Beltrame ◽

Donatella Sciuto ◽

Christina Silvano

Keyword(s):

System On Chip ◽

Power Efficient ◽

On Chip

Download Full-text

Human++: Emerging Technology for Body Area Networks

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip ◽

10.1007/978-0-387-74909-9_21 ◽

2007 ◽

pp. 377-397 ◽

Cited By ~ 4

Author(s):

Julien Penders ◽

Bert Gyselinckx ◽

Ruud Vullers ◽

Olivier Rousseaux ◽

Mladen Berekovic ◽

...

Keyword(s):

Body Area Networks ◽

Emerging Technology ◽

Body Area

Download Full-text

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer US

Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits

Logic Synthesis of EXOR Projected Sum of Products

Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model

Probabilistic amp; Statistical Design—the Wave of the Future

Oversampled Time Estimation Techniques for Precision Photonic Detectors

Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation

Library Compatible Variational Delay Computation

A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures

Human++: Emerging Technology for Body Area Networks

Export Citation Format

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on ChipLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer US

Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits

Logic Synthesis of EXOR Projected Sum of Products

Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model

Probabilistic amp; Statistical Design—the Wave of the Future

Oversampled Time Estimation Techniques for Precision Photonic Detectors

Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation

Library Compatible Variational Delay Computation

A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures

Human++: Emerging Technology for Body Area Networks

IFIP International Federation for Information Processing - VLSI-SoC: Research Trends in VLSI and Systems on Chip
Latest Publications