[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems
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Published By IEEE Comput. Soc. Press

0818624574

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Hex-repair: a new approach to hexagonal array reconfiguration

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199971 ◽

2002 ◽

Cited By ~ 1

Author(s):

R. Venkateswaran ◽

P. Mazumder ◽

Kang G. Shin

Keyword(s):

Hexagonal Array ◽

New Approach

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Harvest rate of reconfigurable pipelines

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199949 ◽

2002 ◽

Author(s):

Weiping Shi ◽

Ming-Feng Chang ◽

W. Kent Fuchs

Keyword(s):

Harvest Rate

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Concurrent error diagnosis in mesh array architectures based on overlapping H-processes

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199955 ◽

2002 ◽

Author(s):

E.S. Manolakos ◽

D. Dakhil ◽

M. Vai

Keyword(s):

Error Diagnosis

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Current-mode techniques for analog VLSI: technology and defect tolerance issues

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199942 ◽

2002 ◽

Cited By ~ 3

Author(s):

A.G. Andreou

Keyword(s):

Current Mode ◽

Analog Vlsi ◽

Defect Tolerance ◽

Vlsi Technology

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Concurrent built-in self-test with reduced fault latency

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199965 ◽

2002 ◽

Author(s):

Y.-N. Shen ◽

F. Lombardi

Keyword(s):

Self Test ◽

Built In Self Test

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A bottom-up methodology to characterize delay faults

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199961 ◽

2002 ◽

Cited By ~ 4

Author(s):

J. Zubairi ◽

G.L. Craig

Keyword(s):

Delay Faults ◽

Bottom Up

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Array architecture for ATG with 100% fault coverage

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199966 ◽

2002 ◽

Cited By ~ 6

Author(s):

K. El-Ayat ◽

R. Cahn ◽

Chung Lau Chan ◽

T. Speers

Keyword(s):

Fault Coverage ◽

Array Architecture

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Physical boundaries of performance: the interconnection perspective

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199967 ◽

2002 ◽

Cited By ~ 1

Author(s):

S.K. Tewksbury

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Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199947 ◽

2002 ◽

Cited By ~ 3

Author(s):

J. Hammond ◽

G. Sery

Keyword(s):

Process Development ◽

Production Yield ◽

Large Array ◽

Yield Improvement ◽

Very Large Array ◽

Knowledge Based

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Reliability evaluation of FUSS and other reconfiguration schemes

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems ◽

10.1109/dftvs.1991.199956 ◽

2002 ◽

Author(s):

N. Lopez-Benitez ◽

M. Chean

Keyword(s):

Reliability Evaluation

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[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Hex-repair: a new approach to hexagonal array reconfiguration

Harvest rate of reconfigurable pipelines

Concurrent error diagnosis in mesh array architectures based on overlapping H-processes

Current-mode techniques for analog VLSI: technology and defect tolerance issues

Concurrent built-in self-test with reduced fault latency

A bottom-up methodology to characterize delay faults

Array architecture for ATG with 100% fault coverage

Physical boundaries of performance: the interconnection perspective

Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement

Reliability evaluation of FUSS and other reconfiguration schemes

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems
Latest Publications