2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)

An efficient real-time data pipeline for the CHIME Pathfinder radio telescope X-engine

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245705 ◽

2015 ◽

Cited By ~ 5

Author(s):

Andre Recnik ◽

Kevin Bandura ◽

Nolan Denman ◽

Adam D. Hincks ◽

Gary Hinshaw ◽

...

Keyword(s):

Real Time ◽

Radio Telescope ◽

Time Data ◽

Data Pipeline ◽

Real Time Data

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Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245732 ◽

2015 ◽

Cited By ~ 1

Author(s):

Erkan Diken ◽

Martin J. O'Riordan ◽

Roel Jordans ◽

Lech Jozwiak ◽

Henk Corporaal ◽

...

Keyword(s):

Code Generation ◽

Vliw Architectures

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Dual-rail active protection system against side-channel analysis in FPGAs

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245707 ◽

2015 ◽

Author(s):

Wei He ◽

Dirmanto Jap

Keyword(s):

Protection System ◽

Side Channel ◽

Side Channel Analysis ◽

Active Protection ◽

Channel Analysis

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[Front cover]

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245688 ◽

2015 ◽

Keyword(s):

Front Cover

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Custom FPGA-based soft-processors for sparse graph acceleration

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245698 ◽

2015 ◽

Cited By ~ 12

Author(s):

Nachiket Kapre

Keyword(s):

Sparse Graph

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Noxim: An open, extensible and cycle-accurate network on chip simulator

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245728 ◽

2015 ◽

Cited By ~ 92

Author(s):

Vincenzo Catania ◽

Andrea Mineo ◽

Salvatore Monteleone ◽

Maurizio Palesi ◽

Davide Patti

Keyword(s):

Network On Chip ◽

On Chip

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GPU kernels for high-speed 4-bit astrophysical data processing

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245729 ◽

2015 ◽

Cited By ~ 4

Author(s):

Peter Klages ◽

Kevin Bandura ◽

Nolan Denman ◽

Andre Recnik ◽

Jonathan Sievers ◽

...

Keyword(s):

Data Processing ◽

High Speed ◽

Astrophysical Data

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MultiExplorer: A tool set for multicore system-on-chip design exploration

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245727 ◽

2015 ◽

Cited By ~ 1

Author(s):

Rodrigo Devigo ◽

Liana Duenha ◽

Rodolfo Azevedo ◽

Ricardo Santos

Keyword(s):

System On Chip ◽

Chip Design ◽

Design Exploration ◽

Multicore System ◽

Tool Set ◽

On Chip

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An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2015.7245709 ◽

2015 ◽

Cited By ~ 11

Author(s):

Bingzhe Li ◽

M. Hassan Najafi ◽

David J. Lilja

Keyword(s):

Fpga Implementation ◽

Restricted Boltzmann Machine ◽

Boltzmann Machine

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2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

An efficient real-time data pipeline for the CHIME Pathfinder radio telescope X-engine

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths

Table of contents

Dual-rail active protection system against side-channel analysis in FPGAs

[Front cover]

Custom FPGA-based soft-processors for sparse graph acceleration

Noxim: An open, extensible and cycle-accurate network on chip simulator

GPU kernels for high-speed 4-bit astrophysical data processing

MultiExplorer: A tool set for multicore system-on-chip design exploration

An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

Export Citation Format

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

An efficient real-time data pipeline for the CHIME Pathfinder radio telescope X-engine

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths

Table of contents

Dual-rail active protection system against side-channel analysis in FPGAs

[Front cover]

Custom FPGA-based soft-processors for sparse graph acceleration

Noxim: An open, extensible and cycle-accurate network on chip simulator

GPU kernels for high-speed 4-bit astrophysical data processing

MultiExplorer: A tool set for multicore system-on-chip design exploration

An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Latest Publications