Proceedings The Seventh IEEE European Test Workshop
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Published By IEEE Comput. Soc

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Silicon technology advances and implications on test

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029632 ◽

2005 ◽

Author(s):

G. Spirakis

Keyword(s):

Silicon Technology ◽

Technology Advances

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On selecting testable paths in scan designs

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029639 ◽

2003 ◽

Cited By ~ 11

Author(s):

Yun Shao ◽

S.M. Reddy ◽

I. Pomeranz ◽

S. Kajihara

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A real world application used to implement a true IDDQ based test strategy (facts and figures)

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029643 ◽

2003 ◽

Cited By ~ 5

Author(s):

H. Manhaeve ◽

J.S. Vaccaro ◽

L. Benecke ◽

D. Prystasz

Keyword(s):

Real World ◽

Test Strategy ◽

Real World Application

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Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029645 ◽

2003 ◽

Cited By ~ 4

Author(s):

M.J. Burbidge ◽

F. Poullet ◽

J. Tijou ◽

A. Richardson

Keyword(s):

Charge Pump

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ATPG for timing-induced functional errors on trigger events in hardware-software systems

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029635 ◽

2003 ◽

Cited By ~ 2

Author(s):

S. Arekapudi ◽

Fei Xin ◽

Jinzheng Peng ◽

I.G. Harris

Keyword(s):

Software Systems ◽

Trigger Events

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Combining deterministic logic BIST with test point insertion

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029646 ◽

2003 ◽

Cited By ~ 5

Author(s):

H. Vranken ◽

F. Meister ◽

H.-J. Wunderlich

Keyword(s):

Test Point ◽

Test Point Insertion ◽

Logic Bist

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Power constrained preemptive TAM scheduling

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029648 ◽

2003 ◽

Cited By ~ 20

Author(s):

E. Larsson ◽

H. Fujiwara

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Dependable testing of compactor MISR: an imperceptible problem?

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029636 ◽

2003 ◽

Cited By ~ 3

Author(s):

A. Hlawiczka ◽

M. Kopec

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A novel test time reduction algorithm for test architecture design for core-based system chips

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029633 ◽

2003 ◽

Cited By ~ 6

Author(s):

S.K. Goel ◽

E.J. Marinissen

Keyword(s):

Test Time ◽

Architecture Design ◽

Reduction Algorithm ◽

Test Time Reduction ◽

Time Reduction ◽

Test Architecture

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A high accuracy triangle-wave signal generator for on-chip ADC testing

Proceedings The Seventh IEEE European Test Workshop ◽

10.1109/etw.2002.1029644 ◽

2003 ◽

Cited By ~ 37

Author(s):

S. Bernard ◽

F. Azais ◽

Y. Bertrand ◽

M. Renovell

Keyword(s):

High Accuracy ◽

Signal Generator ◽

Wave Signal ◽

On Chip ◽

Adc Testing

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Proceedings The Seventh IEEE European Test WorkshopLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Silicon technology advances and implications on test

On selecting testable paths in scan designs

A real world application used to implement a true IDDQ based test strategy (facts and figures)

Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's

ATPG for timing-induced functional errors on trigger events in hardware-software systems

Combining deterministic logic BIST with test point insertion

Power constrained preemptive TAM scheduling

Dependable testing of compactor MISR: an imperceptible problem?

A novel test time reduction algorithm for test architecture design for core-based system chips

A high accuracy triangle-wave signal generator for on-chip ADC testing

Proceedings The Seventh IEEE European Test Workshop
Latest Publications