2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
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9781538637975

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Power-efficient and highly scalable parallel graph sampling using FPGAs

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279806 ◽

2017 ◽

Cited By ~ 1

Author(s):

Usman Tariq ◽

Umer I. Cheema ◽

Fahad Saeed

Keyword(s):

Power Efficient ◽

Graph Sampling ◽

Parallel Graph

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Glitch-aware variable pipeline optimization for CGRAs

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279797 ◽

2017 ◽

Cited By ~ 2

Author(s):

Takuya Kojima ◽

Naoki Ando ◽

Hayate Okuhara ◽

Hideharu Amano

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Fine-grained on-line power monitoring for soft microprocessor based system-on-chip

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279794 ◽

2017 ◽

Author(s):

Young H. Cho ◽

Siddharth S. Bhargav

Keyword(s):

System On Chip ◽

Power Monitoring ◽

Fine Grained ◽

On Line ◽

On Chip

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Horizontal address-bit DPA against montgomery kP implementation

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279800 ◽

2017 ◽

Cited By ~ 5

Author(s):

Ievgen Kabin ◽

Zoya Dyka ◽

Dan Kreiser ◽

Peter Langendoerfer

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Trusted display and input using screen overlays

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279826 ◽

2017 ◽

Cited By ~ 3

Author(s):

Anthony Brandon ◽

Michael Trimarchi

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Fast generation of high throughput customized deep learning accelerators on FPGAs

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279792 ◽

2017 ◽

Cited By ~ 8

Author(s):

Hanqing Zeng ◽

Chi Zhang ◽

Viktor Prasanna

Keyword(s):

Deep Learning ◽

High Throughput

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HGum: Messaging framework for hardware accelerators

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279799 ◽

2017 ◽

Cited By ~ 1

Author(s):

Sizhuo Zhang ◽

Hari Angepat ◽

Derek Chiou

Keyword(s):

Hardware Accelerators

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Aging resilient RO PUF with increased reliability in FPGA

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279773 ◽

2017 ◽

Author(s):

Sreeja Chowdhury ◽

Xiaolin Xu ◽

Mark Tehranipoor ◽

Domenic Forte

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HW/SW co-design experimental framework using configurable SoCs

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279801 ◽

2017 ◽

Cited By ~ 1

Author(s):

Siyuan Xu ◽

Jianqi Chen ◽

Benjamin Carrion Schafer

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Adaptive software-augmented hardware reconfiguration with dataflow design automation

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) ◽

10.1109/reconfig.2017.8279772 ◽

2017 ◽

Author(s):

Claudio Rubattu ◽

Francesca Palumbo ◽

Maxime Pelcat

Keyword(s):

Design Automation ◽

Adaptive Software ◽

Hardware Reconfiguration

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2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Power-efficient and highly scalable parallel graph sampling using FPGAs

Glitch-aware variable pipeline optimization for CGRAs

Fine-grained on-line power monitoring for soft microprocessor based system-on-chip

Horizontal address-bit DPA against montgomery kP implementation

Trusted display and input using screen overlays

Fast generation of high throughput customized deep learning accelerators on FPGAs

HGum: Messaging framework for hardware accelerators

Aging resilient RO PUF with increased reliability in FPGA

HW/SW co-design experimental framework using configurable SoCs

Adaptive software-augmented hardware reconfiguration with dataflow design automation

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Latest Publications