2009 IEEE International Symposium on Performance Analysis of Systems and Software
Latest Publications

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9781424441846

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User- and process-driven dynamic voltage and frequency scaling

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919634 ◽

2009 ◽

Cited By ~ 16

Author(s):

Bin Lin ◽

Arindam Mallik ◽

Peter Dinda ◽

Gokhan Memik ◽

Robert Dick

Keyword(s):

Frequency Scaling ◽

Dynamic Voltage

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Understanding the cost of thread migration for multi-threaded Java applications running on a multicore platform

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919644 ◽

2009 ◽

Cited By ~ 3

Author(s):

Qiming Teng ◽

Peter F. Sweeney ◽

Evelyn Duesterwald

Keyword(s):

Thread Migration ◽

The Cost

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Analyzing the impact of on-chip network traffic on program phases for CMPs

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919653 ◽

2009 ◽

Cited By ~ 3

Author(s):

Yu Zhang ◽

Berkin Ozisikyilmaz ◽

Gokhan Memik ◽

John Kim ◽

Alok Choudhary

Keyword(s):

Network Traffic ◽

On Chip ◽

The Impact

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SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919654 ◽

2009 ◽

Author(s):

Jeff Ringenberg ◽

Trevor Mudge

Keyword(s):

Assembly Code

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2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919631 ◽

2009 ◽

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Online compression of cache-filtered address traces

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919650 ◽

2009 ◽

Cited By ~ 1

Author(s):

Pierre Michaud

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Accuracy of performance counter measurements

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919635 ◽

2009 ◽

Cited By ~ 39

Author(s):

Dmitrijs Zaparanuks ◽

Milan Jovic ◽

Matthias Hauswirth

Keyword(s):

Performance Counter

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Accelerating architecture research

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919629 ◽

2009 ◽

Cited By ~ 2

Author(s):

Joel Emer

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Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919646 ◽

2009 ◽

Cited By ~ 4

Author(s):

Jeffrey J. Cook ◽

Craig Zilles

Keyword(s):

Dna Sequence ◽

De Novo ◽

Sequence Assembly ◽

Short Read ◽

Dna Sequence Assembly ◽

Memory Footprint

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An analytic model of optimistic Software Transactional Memory

2009 IEEE International Symposium on Performance Analysis of Systems and Software ◽

10.1109/ispass.2009.4919647 ◽

2009 ◽

Cited By ~ 11

Author(s):

Armin Heindl ◽

Gilles Pokam ◽

Ali-Reza Adl-Tabatabai

Keyword(s):

Transactional Memory ◽

Software Transactional Memory ◽

Analytic Model

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2009 IEEE International Symposium on Performance Analysis of Systems and Software
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

User- and process-driven dynamic voltage and frequency scaling

Understanding the cost of thread migration for multi-threaded Java applications running on a multicore platform

Analyzing the impact of on-chip network traffic on program phases for CMPs

SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code

Table of contents

Online compression of cache-filtered address traces

Accuracy of performance counter measurements

Accelerating architecture research

Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly

An analytic model of optimistic Software Transactional Memory

Export Citation Format

2009 IEEE International Symposium on Performance Analysis of Systems and SoftwareLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

User- and process-driven dynamic voltage and frequency scaling

Understanding the cost of thread migration for multi-threaded Java applications running on a multicore platform

Analyzing the impact of on-chip network traffic on program phases for CMPs

SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code

Table of contents

Online compression of cache-filtered address traces

Accuracy of performance counter measurements

Accelerating architecture research

Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly

An analytic model of optimistic Software Transactional Memory

2009 IEEE International Symposium on Performance Analysis of Systems and Software
Latest Publications