Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14
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9781450330503

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A high-level model of embedded flash energy consumption

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656108 ◽

2014 ◽

Cited By ~ 6

Author(s):

James Pallister ◽

Kerstin Eder ◽

Simon J. Hollis ◽

Jeremy Bennett

Keyword(s):

Energy Consumption ◽

Level Model ◽

High Level ◽

Embedded Flash

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The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656130 ◽

2014 ◽

Cited By ~ 12

Author(s):

Bilel Belhadj ◽

Alexandre Valentian ◽

Pascal Vivet ◽

Marc Duranton ◽

Liqiang He ◽

...

Keyword(s):

3D Stacking

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A system-level simulation framework for evaluating task migration in MPSoCs

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656111 ◽

2014 ◽

Cited By ~ 10

Author(s):

Wei Quan ◽

Andy D. Pimentel

Keyword(s):

System Level ◽

Simulation Framework ◽

Task Migration ◽

System Level Simulation

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Context-sensitive timing simulation of binary embedded software

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656117 ◽

2014 ◽

Cited By ~ 10

Author(s):

Sebastian Ottlik ◽

Stefan Stattelmann ◽

Alexander Viehl ◽

Wolfgang Rosenstiel ◽

Oliver Bringmann

Keyword(s):

Embedded Software ◽

Context Sensitive ◽

Timing Simulation

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SDCTune

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656127 ◽

2014 ◽

Cited By ~ 18

Author(s):

Qining Lu ◽

Karthik Pattabiraman ◽

Meeta S. Gupta ◽

Jude A. Rivers

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Construction of GCCFG for inter-procedural optimizations in software managed manycore (SMM) architectures

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656122 ◽

2014 ◽

Cited By ~ 2

Author(s):

Bryce Holton ◽

Ke Bai ◽

Aviral Shrivastava ◽

Harini Ramaprasad

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Splitting functions into single-entry regions

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656128 ◽

2014 ◽

Cited By ~ 4

Author(s):

Stefan Hepp ◽

Florian Brandner

Keyword(s):

Single Entry

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A low-cost memory interface for high-throughput accelerators

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656109 ◽

2014 ◽

Cited By ~ 3

Author(s):

Jing Huang ◽

Yuanjie Huang ◽

Olivier Temam ◽

Paolo Ienne ◽

Yunji Chen ◽

...

Keyword(s):

High Throughput ◽

Low Cost ◽

Memory Interface

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Auto-parallelization of data structure operations for GPUs

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656115 ◽

2014 ◽

Author(s):

Rupesh Nasre

Keyword(s):

Data Structure

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Fault resilient physical neural networks on a single chip

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14 ◽

10.1145/2656106.2656126 ◽

2014 ◽

Cited By ~ 2

Author(s):

Weidong Shi ◽

Yuanfeng Wen ◽

Ziyi Liu ◽

Xi Zhao ◽

Dainis Boumber ◽

...

Keyword(s):

Neural Networks ◽

Single Chip

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Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

A high-level model of embedded flash energy consumption

The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators

A system-level simulation framework for evaluating task migration in MPSoCs

Context-sensitive timing simulation of binary embedded software

SDCTune

Construction of GCCFG for inter-procedural optimizations in software managed manycore (SMM) architectures

Splitting functions into single-entry regions

A low-cost memory interface for high-throughput accelerators

Auto-parallelization of data structure operations for GPUs

Fault resilient physical neural networks on a single chip

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14
Latest Publications