Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science
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Published By Springer Berlin Heidelberg

9783642009037, 9783642009044

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Complexity Effective Bypass Networks

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_11 ◽

2009 ◽

pp. 201-221

Author(s):

Aneesh Aggarwal

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Linux Kernel Compaction through Cold Code Swapping

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_10 ◽

2009 ◽

pp. 173-200

Author(s):

Dominique Chanet ◽

Javier Cabezas ◽

Enric Morancho ◽

Nacho Navarro ◽

Koen De Bosschere

Keyword(s):

Linux Kernel

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Branch Predictor Warmup for Sampled Simulation through Branch History Matching

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_4 ◽

2009 ◽

pp. 45-64

Author(s):

Simon Kluyskens ◽

Lieven Eeckhout

Keyword(s):

History Matching ◽

Branch Predictor

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Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_2 ◽

2009 ◽

pp. 4-22 ◽

Cited By ~ 2

Author(s):

Georgios Keramidas ◽

Polychronis Xekalakis ◽

Stefanos Kaxiras

Keyword(s):

Power Reduction ◽

Dynamic Power

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Compiler Support for Code Size Reduction Using a Queue-Based Processor

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_14 ◽

2009 ◽

pp. 269-285 ◽

Cited By ~ 2

Author(s):

Arquimedes Canedo ◽

Ben Abderazek ◽

Masahiro Sowa

Keyword(s):

Size Reduction ◽

Code Size ◽

Compiler Support

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Reexecution and Selective Reuse in Checkpoint Processors

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_13 ◽

2009 ◽

pp. 242-268 ◽

Cited By ~ 1

Author(s):

Amit Golander ◽

Shlomo Weiss

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Compiler-Assisted Memory Encryption for Embedded Processors

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_3 ◽

2009 ◽

pp. 23-44

Author(s):

Vijay Nagarajan ◽

Rajiv Gupta ◽

Arvind Krishnaswamy

Keyword(s):

Embedded Processors ◽

Memory Encryption

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Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_9 ◽

2009 ◽

pp. 149-172 ◽

Cited By ~ 3

Author(s):

Minwook Ahn ◽

Yunheung Paek

Keyword(s):

Code Generation ◽

Embedded Processors

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Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_7 ◽

2009 ◽

pp. 107-127

Author(s):

Woojin Choi ◽

Seok-Jun Park ◽

Michel Dubois

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Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science ◽

10.1007/978-3-642-00904-4_6 ◽

2009 ◽

pp. 85-104 ◽

Cited By ~ 2

Author(s):

Chunling Hu ◽

Daniel A. Jiménez ◽

Ulrich Kremer

Keyword(s):

Time Dependent ◽

Event Counter ◽

Edge Vector

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Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer ScienceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

Complexity Effective Bypass Networks

Linux Kernel Compaction through Cold Code Swapping

Branch Predictor Warmup for Sampled Simulation through Branch History Matching

Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

Compiler Support for Code Size Reduction Using a Queue-Based Processor

Reexecution and Selective Reuse in Checkpoint Processors

Compiler-Assisted Memory Encryption for Embedded Processors

Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers

Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors

Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization

Transactions on High-Performance Embedded Architectures and Compilers II - Lecture Notes in Computer Science
Latest Publications