2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV)
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9781538633779

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Development of a smart IoT device for bicyclists

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188640 ◽

2017 ◽

Author(s):

Masaki Saegusa ◽

Koyo Katsura

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[Copyright notice]

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188614 ◽

2017 ◽

Keyword(s):

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2 × VDD 28-nm CMOS digital output buffer using low-Vth transistors for slew rate adjustment

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188630 ◽

2017 ◽

Author(s):

Chua-Chin Wangt ◽

Tsung-Yi Tsai ◽

Yu-Lin Deng ◽

Tzung-Je Lee

Keyword(s):

Output Buffer ◽

Slew Rate ◽

Digital Output ◽

Rate Adjustment ◽

28 Nm

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A low power complementary organic double-edge triggered D flip-flop with variable threshold voltage transistors

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188651 ◽

2017 ◽

Author(s):

Tung Xuan Pham ◽

Huyen Thanh Pham ◽

Toan Thanh Dao

Keyword(s):

Low Power ◽

Threshold Voltage ◽

Flip Flop ◽

Variable Threshold ◽

Double Edge

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16.8 GB/s LPDDR4-3200@32-bit memory access bandwidth

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188629 ◽

2017 ◽

Author(s):

Kha Minh Huynh ◽

Seiji Mochizuki ◽

Thien Thanh Bui Nguyen ◽

Hai Vu Nguyen ◽

Khoa Dac Tran ◽

...

Keyword(s):

Memory Access

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[Keynote] Renesas Design Vietnam-way to a semiconductor solution provider for the next decade from the first successful decade in semiconductor industry of Vietnam

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188626 ◽

2017 ◽

Author(s):

Atsuo Hanami ◽

Kenichi Iwata ◽

Yoshinori Kaneko ◽

Pham Tuong Hai

Keyword(s):

Semiconductor Industry

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Efficient Binary Arithmetic Encoder for HEVC with multiple bypass bin processing

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188644 ◽

2017 ◽

Author(s):

Quang-Linh Nguyen ◽

Dinh-Lam Tran ◽

Duy-Hieu Bui ◽

Duc-Tho Mai ◽

Xuan-Tu Tran

Keyword(s):

Binary Arithmetic

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Verilog-A based compact model of the silicon hall element

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188635 ◽

2017 ◽

Author(s):

Dao Dinh Ha ◽

V. Stempitsky ◽

Tran Tuan Trung

Keyword(s):

Compact Model ◽

Hall Element

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2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188615 ◽

2017 ◽

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Technical program committee

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) ◽

10.1109/icdv.2017.8188623 ◽

2017 ◽

Keyword(s):

Program Committee ◽

Technical Program Committee ◽

Technical Program

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2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Development of a smart IoT device for bicyclists

[Copyright notice]

2 × VDD 28-nm CMOS digital output buffer using low-Vth transistors for slew rate adjustment

A low power complementary organic double-edge triggered D flip-flop with variable threshold voltage transistors

16.8 GB/s LPDDR4-3200@32-bit memory access bandwidth

[Keynote] Renesas Design Vietnam-way to a semiconductor solution provider for the next decade from the first successful decade in semiconductor industry of Vietnam

Efficient Binary Arithmetic Encoder for HEVC with multiple bypass bin processing

Verilog-A based compact model of the silicon hall element

Table of contents

Technical program committee

Export Citation Format

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Development of a smart IoT device for bicyclists

[Copyright notice]

2 × VDD 28-nm CMOS digital output buffer using low-Vth transistors for slew rate adjustment

A low power complementary organic double-edge triggered D flip-flop with variable threshold voltage transistors

16.8 GB/s LPDDR4-3200@32-bit memory access bandwidth

[Keynote] Renesas Design Vietnam-way to a semiconductor solution provider for the next decade from the first successful decade in semiconductor industry of Vietnam

Efficient Binary Arithmetic Encoder for HEVC with multiple bypass bin processing

Verilog-A based compact model of the silicon hall element

Table of contents

Technical program committee

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV)
Latest Publications