Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By Springer Berlin Heidelberg

9783540665595, 9783540481539

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_12 ◽

2010 ◽

pp. 142-157 ◽

Cited By ~ 54

Author(s):

E. Allen Emerson ◽

Richard J. Trefler

Keyword(s):

Model Checking ◽

Symmetry Reduction ◽

New Techniques ◽

Full Symmetry

Download Full-text

Hazard—Freedom Checking in Speed—Independent Systems

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_24 ◽

1999 ◽

pp. 317-321 ◽

Cited By ~ 3

Author(s):

Husnu Yenigun ◽

Vladimir Levin ◽

Doron Peled ◽

Peter A. Beerel

Download Full-text

Exploiting Retiming in a Guided Simulation Based Validation Methodology

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_32 ◽

1999 ◽

pp. 350-355 ◽

Cited By ~ 4

Author(s):

Aarti Gupta ◽

Pranav Ashar ◽

Sharad Malik

Keyword(s):

Simulation Based

Download Full-text

”Have I Written Enough Properties?” - A Method of Comparison Between Specification and Implementation

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_21 ◽

1999 ◽

pp. 280-297 ◽

Cited By ~ 58

Author(s):

Sagi Katz ◽

Orna Grumberg ◽

Danny Geist

Keyword(s):

Specification And Implementation

Download Full-text

Formal Verification of Explicitly Parallel Microprocessors

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_4 ◽

1999 ◽

pp. 23-36 ◽

Cited By ~ 1

Author(s):

Byron Cook ◽

John Launchbury ◽

John Matthews ◽

Dick Kieburtz

Keyword(s):

Formal Verification

Download Full-text

Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_9 ◽

1999 ◽

pp. 99-109 ◽

Cited By ~ 14

Author(s):

Cindy Eisner

Keyword(s):

Model Checking ◽

Symbolic Model Checking ◽

Railway Stations ◽

Symbolic Model

Download Full-text

A Systematic Incrementalization Technique and Its Application to Hardware Design

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_28 ◽

1999 ◽

pp. 334-337 ◽

Cited By ~ 1

Author(s):

Steven D. Johnson ◽

Yanhong A. Liu ◽

Yuchen Zhang

Keyword(s):

Hardware Design

Download Full-text

Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_27 ◽

1999 ◽

pp. 330-333

Author(s):

George Economakos ◽

George Papakonstantinou

Keyword(s):

High Level Synthesis ◽

Attribute Grammars ◽

High Level

Download Full-text

A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_3 ◽

1999 ◽

pp. 8-22 ◽

Cited By ~ 5

Author(s):

Ravi Hosabettu ◽

Ganesh Gopalakrishnan ◽

Mandayam Srivas

Keyword(s):

Proof Of Correctness

Download Full-text

Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/3-540-48153-2_16 ◽

1999 ◽

pp. 202-218 ◽

Cited By ~ 1

Author(s):

Mark D. Aagaard ◽

Thomas F. Melham ◽

John W. O’Leary

Keyword(s):

Theorem Proving

Download Full-text

Lecture Notes in Computer Science - Correct Hardware Design and Verification MethodsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking

Hazard—Freedom Checking in Speed—Independent Systems

Exploiting Retiming in a Guided Simulation Based Validation Methodology

”Have I Written Enough Properties?” - A Method of Comparison Between Specification and Implementation

Formal Verification of Explicitly Parallel Microprocessors

Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard

A Systematic Incrementalization Technique and Its Application to Hardware Design

Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars

A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer

Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods
Latest Publications