2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781538661031

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

EMAXVR: A programmable accelerator employing near ALU utilization to DSA

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373078 ◽

2018 ◽

Cited By ~ 1

Author(s):

Takahiro Ichikura ◽

Ryusuke Yamano ◽

Yuma Kikutani ◽

Renyuan Zhang ◽

Yasuhiko Nakashima

Download Full-text

Message from the program committee chairs

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373068 ◽

2018 ◽

Keyword(s):

Program Committee

Download Full-text

Panel discussions: “Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?”

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373075 ◽

2018 ◽

Author(s):

Koji Inoue ◽

Takuya Araki ◽

Takumi Maruyama ◽

Pritish Narayanan ◽

Takashi Oshima ◽

...

Keyword(s):

Scaling Limits ◽

Power Performance ◽

Performance Improvements ◽

Sustainable Power

Download Full-text

Supporting organization

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373085 ◽

2018 ◽

Download Full-text

Power performance analysis of ARM scalable vector extension

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373083 ◽

2018 ◽

Author(s):

Tetsuya Odajima ◽

Yuetsu Kodama ◽

Mitsuhisa Sato

Keyword(s):

Performance Analysis ◽

Power Performance

Download Full-text

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373084 ◽

2018 ◽

Cited By ~ 1

Author(s):

Kesami Hagiwara ◽

Tomoichi Hayashi ◽

Shumpei Kawasaki ◽

Fumio Arakawa ◽

Oleg Endo ◽

...

Keyword(s):

Two Stage ◽

Robotic Applications

Download Full-text

Message from the steering committee chair

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373067 ◽

2018 ◽

Keyword(s):

Steering Committee ◽

Committee Chair

Download Full-text

Subthreshold logic for low-area and energy efficient true random number generator

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373081 ◽

2018 ◽

Author(s):

Mathieu Coustans ◽

Abdelkarim Cherkaoui ◽

Laurent Fesquet ◽

Christian Terrier ◽

Stephanie Salgado ◽

...

Keyword(s):

Energy Efficient ◽

Random Number ◽

Random Number Generator ◽

Number Generator ◽

True Random Number Generator ◽

Low Area ◽

Subthreshold Logic

Download Full-text

XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373076 ◽

2018 ◽

Cited By ~ 10

Author(s):

Andrawes Al Bahou ◽

Geethan Karunaratne ◽

Renzo Andri ◽

Lukas Cavigelli ◽

Luca Benini

Keyword(s):

Neural Networks ◽

Convolutional Neural Networks ◽

Hardware Accelerator

Download Full-text

Keynote & invited speaker's biography

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips.2018.8373072 ◽

2018 ◽

Download Full-text

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

EMAXVR: A programmable accelerator employing near ALU utilization to DSA

Message from the program committee chairs

Panel discussions: “Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?”

Supporting organization

Power performance analysis of ARM scalable vector extension

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications

Message from the steering committee chair

Subthreshold logic for low-area and energy efficient true random number generator

XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks

Keynote & invited speaker's biography

2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
Latest Publications